The FlexSPI controller configuration (LUT, per-device FLSHCR/DLLCR)
is lost when the controller power domain is powered down. On
PM_DEVICE_ACTION_TURN_ON, reset the memc per-port LUT bookkeeping so
the probe re-allocates LUT slots from zero, then re-run the flash
probe to rebuild the device configuration and LUT from the chip.
Re-running the controller init or wiping the whole LUT is not
possible while the CPU executes XIP from the NOR, so the restore
relies on the ROM FCB controller-level state and replaces (not
clears) the LUT entries the driver owns.
Add memc_flexspi_reset_lut_alloc() to reset the per-port LUT
bookkeeping after a power-domain power-down.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Tested:
Verified that reading and writing data to the PSRAM
with MCU's FlexSPI controller in Quad Mode, works as
expected.
Signed-off-by: Nikhil Namjoshi <nikhilnamjoshi@google.com>
Enable this kconfig setting to force using a specific raw value for the
OVRDVAL field in the DLLCR registers.
This option gives more granularity than the 'data-valid-time' field in
the dts. The unit of 'data-valid-time' is nanoseconds while the unit of
OVRDVAL are raw delay cells.
Normally the 'data-valid-time' on any 'nxp,imx-flexspi-device' device
will set the OVRDVAL and OVRDEN fields in the DLLCR register
but works only when the 'rx-clock-source' is configured to '#0 External
input from DQS pad' and the frequency <= 100MHz.
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
Flexram is really not a memory controller, and does not belong in memc
namespace or directory. Move it to it's own misc directory and remove
memc_ from the namespace.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add support for initializing the FLEXSPI when using a flash attached to
the FLEXSPI for XIP. This option is guarded behind a Kconfig, as
enabling it is dangerous and requires special care be taken by the user
to ensure that the configuration of pins and FLEXSPI settings will not
break support for reading the attached flash, as this will break XIP
support.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use custom initialization priority for FLEXSPI MEMC driver. This may be
needed when the MEMC driver must initialize before a flash driver, and
before another MEMC driver (for an attached device, like PSRAM)
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add driver for IS66WVQ8M4 PSRAM, using the MCUX FlexSPI interface to
write data to the PSRAM device.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The MCUX platform always uses pinctrl, there's no need to keep extra
macrology around pinctrl. Also updated driver's Kconfig options to
`select PINCTRL` (note that some already did).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Introduce driver for APS6408L PSRAM, built on top of the MCUX memc
driver for flexSPI. This driver supports operating the PSRAM in high
speed mode (200MHz or more). Note that in order to support this
PSRAM's alignment requirements, either ahb-read-addr-opt or
ahb-prefetch must be set for the FlexSPI instance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Rename flexspi-hyperram driver to flexspi-s27ks0641, and update
function names. This driver is only capable of supporting the
s27ks0641 HyperRAM chip, as the lookup table given in this driver
is specific to the s27ks0641.
Rename the flexspi-hyperram binding to reflect this, to
prevent confusion from users.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update memc drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.
We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.
Signed-off-by: Kumar Gala <galak@kernel.org>
Initially the flexspi device only supported a flash driver for
external NOR flash. As the controller supports HyperBus devices,
which can be either volatile or non-volatile, the driver iss moved
to drivers/memc.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
