Commit graph

11 commits

Author SHA1 Message Date
Anas Nashif d7678f1694 xtensa: move to use system cache API support for coherency
Remove custom implementation and use system cache interface instead.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-02-03 13:42:33 -05:00
Flavio Ceolin eeea26d206 ipm: cavs: Fix possible buffer overflow
A buffer overflow happens in send() when size is negative because
it is promoted to signed when used in memcpy.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-09-27 11:51:34 -05:00
Andrey Borisovich 23b3cae1b1 inte_adsp: ipc: prevent ipc message send during Device power transition
When CONFIG_PM_DEVICE is enabled IPC Device may be during power transition
during a call to intel_adsp_ipc_send_message function.
Changed signatures of intel_adsp_ipc_send_message and its sync version
to return int and negative error codes on error.
On attempt to send IPC message during Device power transition
-ESHUTDOWN error code is returned, on busy state -EBUSY.
Updated all function references.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2023-06-22 06:14:57 -04:00
Anas Nashif 3db1c59f44 ipm: intel_adsp: use memory window from DTS
Use memory window setup from DTS.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-11 08:28:25 -04:00
Anas Nashif 9cd53958ce intel_adsp: mem_window: rename defines CAVS_ -> ADSP_
Fix namespacing of memory window defines. Not all platforms are CAVS
based anymore.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-11 08:28:25 -04:00
Andrey Borisovich 2e04bfdfe0 soc: intel_adsp: Refactored IPC/IDC
Changes to code:
1. Renamed CAVS_IPC API from common/include/cavs_ipc.h to
common/include/intel_adsp_ipc.h. Renamed all API functions and structs -
added "intel_adsp_" prefix.
2. Moved definitions from intel-ipc-regs.h and ace-ipc-regs.g to SOC
specific headers include/<soc_name>/adsp_ipc_regs.h.
3. Added new common intel_adsp_ipc_devtree.h header with new
macros to retrieve IPC and IDC nodes and register addresses.
Put those new macros in code replacing hardcoded values outside of
devicetree.
4. Changed documentation of IDC and renamed IDC register struct
to have common name between all intel adsp socs.
5. Removed excessive docs description on cAVS IPC protocol.

Changes to Devicetree:
1. Renamed in all CAVS boards .dtsi files content in IPC nodes:
   - "cavs_host_ipc" node labels to "adsp_ipc" labels.
   - compatible "intel,cavs-host-ipc" renamed to
     "intel,adsp-host-ipc".
2. Added (previously missing) yaml file for "intel,adsp-host-ipc"
   compatible.
3. Renamed in all CAVS boards .dtsi files content in IDC nodes:
   - "idc" node labels to "adsp_idc" labels.
   - compatible "intel,cavs-idc" renamed to "intel-adsp-idc"
4. Renamed intel,cavs_idc.yaml file to intel,adsp_idc.yaml
   so it is suitable for both CAVS and ACE SoC family.
   Moved it from ipm bindings to ipc bindings where it belongs.

Changes to Kconfig:
1. Renamed existing Kconfig option CONFIG_CAVS_IPC to
   INTEL_ADSP_IPC.
2. For renamed INTEL_ADSP_IPC addded default value based on
   status of the "adsp-ipc" and "adsp-ipc" node.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-09-02 08:18:32 -04:00
Anas Nashif af3d5331a1 intel-adsp: migrate cavs-mem.h to adsp_memory.h
Move header and make it soc specific.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Anas Nashif 423264b96b intel_adsp: make shim header soc specific
using once single header to support multiple socs and product
generations is error prone and not easily maintained.

Over time we have been adding conditional code in headers and extending
structs  to support new HW features which becomes a problem.

Goal is to keep platform headers in sync with hardware specification and
allow of introduction of new platforms and hardware features by just
introducing a new SoC with its own set of headers.

This is now just a copy of existing cavs-shim.h with slight changes,
goal is to clean this up long term and sync with hardware datasheets and
align on naming as well.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-21 17:55:41 -04:00
Gerard Marull-Paretas fb60aab245 drivers: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:58:21 +02:00
Nazar Kazakov f483b1bc4c everywhere: fix typos
Fix a lot of typos

Signed-off-by: Nazar Kazakov <nazar.kazakov.work@gmail.com>
2022-03-18 13:24:08 -04:00
Andy Ross 27a59ec9d5 drivers/ipm: Add ipm_cavs_host: host/DSP communication on adsp_intel
Intel Audio DSPs have "IPC" interrupt delivery and shared memory
window hardware.  The Sound Open Firmware project has historically
used the combination of these to implement a bidirectional
message-passing interface.  As it happens, this protocol is an
excellent fit for Zephyr's somewhat geriatric but still useful IPM
interface.

This implements a SOF-protocol-compatible transport that will
hopefully prove a bit more futureproof for non-Intel SOF
architectures.  It is a software-only device, built on top of the
underlying SOC APIs for the SRAM windows (in cavs-shim) and IPC
(cavs_ipc).

Note that SOF actually has two protocol variants (ipc3 and ipc4): in
both, the command header (passed as the "id" parameter in IPM) is sent
via the hardware doorbell register.  But in ipc4, the second hardware
scratch register is used to transmit the first four bytes of the
command before involving the SRAM window (in ipc3, it's ignored).
Both modes are supported by this driver, set IPM_CAVS_HOST_REGWORD to
choose the "ipc4" variant.

Finally: note that the memory layout for the windows in question is
inherited from SOF, and for compatibility (with both SOF and with the
offsets used by the host!) these can't be changed without major
surgery.  They're defined in kconfig, but should be treated as
read-only until we get a chance to rework the way Zephyr does its SRAM
window management (and probably in concert with the host drivers).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-03-01 09:59:15 -05:00