Use a default priority to avoid Kconfig blocking when priority
is not set in SoC or Board.
Change-Id: I4edda47b955a7ee834f04dc40d0decbd8dee6305
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change terminology and use SoC instead of platform. An SoC provides
features and default configurations available with an SoC. A board
implements the SoC and adds more features and IP block specific to the
board to extend the SoC functionality such as sensors and debugging
features.
Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
1. Need to unmask interrupts for the sensor subsystem.
2. The GPIO controllers need their clock enabled before they can
start sending out interrupts.
3. Setting up ISR on ARC requires usage of irq_connect().
Change-Id: I633b07292f11e5c5e768fc51fabb70769d407609
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.
Change-Id: Ia0a069464392714f38037841de52e8d265fa4f49
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Now that i2c_transfer/i2c_read/i2c_write are fully synchronous, no need
to use the polling based function.
Change-Id: Ib578cf4a6d72ad0817e1aaeebc7e4dab9f9d293f
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Removes the 'priority' parameter from the IRQ_CONFIG macro.
This parameter was not used anymore in any architecture.
The priority is handled in the IRQ_CONNECT macro.
The documentation is updated as well.
Change-Id: I24a293c5e41bd729d5e759113e0c4a8a6a61e0dd
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Adds io/aux register support for IP configuration.
x86 and ARM configure IP through MMIO register access.
ARC architecture configure IP through io/aux register access.
Change-Id: I4d07b91af09d88b7eb6ac1aa02e875dcd626bd26
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Static irq api expect to have an isr with signature
void isr(void *arg).
This fixes the warning messages due the difference on
the isr parameter.
Change-Id: I64099ce47ba481b40446d5fb7e35fce0e46a9624
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
BIT() is already defined as a generic utility macro in misc/util.h
Change-Id: Ie74bbfe657de5de980439e30b2dcbb9168b69257
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This is currently valid for quark_se platform. It's used internally to
suspend and/or resume the gpio controller.
Change-Id: I5147568ba6b0450363566b5f9fd2e8aa7e41df49
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Change-Id: Ie58e8611a8fe9edec9ebcb123532a97f396098f4
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
There is no such feature per-pin. LS_SYNC is set or unset for the whole
controller.
Change-Id: Ic67048e29a9cc25a19e6a7bcc11d21dd1e65be61
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This platform if actually a subsystem of the Quark SE SoC and is
not standalone. Use a more descriptive name and remove the architecture
from the platform name.
Change-Id: I16b1ab8dd668441683b07fc4512c219924463441
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Put initialization priorities as device driver Kconfig
parameter.
Initialization priority value for each platform is defined
in the platform Kconfig file.
Drivers and platform code use SYS_DEFINE_DEVICE to add
and initialization function.
Change-Id: I2f4f3c7370dac02408a1b50a0a1bade8b427a282
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not depend on environment variables and use a kconfig variable
for defining the architecture.
In addition, remove the X86_32 variable, it just duplicates X86 for
not good reason, at least until start supporting MCUs with 64bit.
Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
SYS_GET_DEVICE() needs the name set in DECLARE_DEVICE_INIT_CONFIG() not
the one in IRQ_CONNECT_STATIC().
Change-Id: Id1ed66953c863531411b34594ffed669ad524ef5
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
That fixes a build error. Platfom's board.h have to provide such flags
if they enable dw gpio 1 controller.
Take the opportunity to provide the right isr to IRQ_CONNECT_STATIC.
Change-Id: I16900ea04f7f7c5d3c99b93a92b00c1f651494de
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Adds the register definition for the DW GPIO hardware block.
This set of registers and offsets are specific for the SS
GPIO hardware block in the Quark SE platform.
In particular, the register BOTHEDGE (offset 0x68 in the
main GPIO block) does not exist on the SS GPIO block.
Change-Id: I4e16ec7c8e89015be1fc8bcdb1b7fa5377890b9d
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
since we are in the same directory, include the file directly.
Change-Id: I21c959538e4a3d9e3fba99eaa9b09697fffe25b0
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Flags allow passing IRQ triggering option for x86 architecture.
Each platform defines flags for a particular device and then
device driver uses them when registers the interrupt handler.
The change in API means that device drivers and sample
applications need to use the new API.
IRQ triggering configuration is now handled by device drivers
by using flags passed to interrupt registering API:
IRQ_CONNECT_STATIC() or irq_connect()
Change-Id: Ibc4312ea2b4032a2efc5b913c6389f780a2a11d1
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Such controller is found in legacy bridge on Intel's platforms. Such as
Poulsbo or Quark x1000.
Change-Id: I30f205f1e73aaa680092e92717fdacbb74046fa3
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Now make use of sys_io_clear_bit and sys_io_set_bit
Change-Id: I11ebcd8c31d2a4c6d3dac37a0eca0ffcfacead61
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
A tiny fix where the pin is the bit position, not its mask.
Change-Id: I4ed8c4b2968ff28b407cab88903351bafe6501ba
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
ioapic_mkstub applies only when an IOAPIC is available in the platform.
Change-Id: I40294e4c11ef04739a1ce2146d125f3c5478013d
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
This patch updates the ISR initialization code to reflect recent
changes in the underlying Zephyr ISR infrastructure. It also adds
assertions to detect failures to lookup device bindings during
initialization.
Change-Id: I4bf1955da44a97f8c2652b96a390804c5cea73e3
Signed-off-by: Michael LeMay <michael.lemay@intel.com>
use gpio_dw instead of gpio_<function>_dw to be consistent in the
driver itself and with other drivers.
Change-Id: Ifb0e50c230f142197eb4b01c1bb4ce1c16e4753f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We now have BIT defined in a header file globally, so lets use it.
Change-Id: Ie7b87478cb5a9e977ec045efa072d28fab86e78b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Allows to remove the both edges support from the DW GPIO driver.
Change-Id: I9e39cca320aeac5d10aafe7a83641917ad004fe6
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Changes the default IRQ priority level from 0 to 2 for the following
kernel configuration options as priorities 0 and 1 are reserved for the
first 32 IDT entries.
SHARED_IRQ_0_PRI
SHARED_IRQ_1_PRI
I2C_DW_0_INT_PRIORITY
GPIO_DW_0_PRI
GPIO_DW_1_PRI
SPI_INTEL_PORT_0_PRI
SPI_INTEL_PORT_1_PRI
Change-Id: I0fc821c68156eb1e1fe776b2bd4ff5890bba40e8
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
This patch corrects gpio_dw_setup to use the MMIO base address
determined by PCI enumeration when that enumeration feature is enabled
instead of always using the default base address specified at compile
time.
Change-Id: If139c40ce30275694e01196a4a4aa529cd714f06
Signed-off-by: Michael LeMay <michael.lemay@intel.com>
Change-Id: I34a54230bc4a63c8a4391d03ff530835910c3705
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In order to have drivers that are usable cross architecture the
signature for IRQ_CONFIG needs to be the same to avoid #ifdef hell in
the driver code based on architecture.
Update the macro and it usage for existing drivers
Change-Id: I22e142b21d4e984add231d1dbd97020e4823985f
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The naming convention used in the source is for there to be an
_ and not a - in the file. Fixing GPIO to be consistent with
the os naming conventions.
Change-Id: Ifc4356c14b52e2cc2411a7445b44c7cb57d2765c
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Gets rid of the trailing initialization level character from the
name of the device variable generated by the macro, since it serves
no useful purpose. (The linker scripts place the various initialization
sections in ascending order based on the name of the section, so there
is no need to embed the initialization level in the variable name itself.)
Change-Id: I56bb79a513b8f77fb1f3fbaccec14454c2520772
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Change all the Intel and Wind River code license from BSD-3 to Apache 2.
Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The newly introduced i2c_poll_transfer() is now used for register
read for PCAL9535A GPIO driver. The old write then read does not
work because every read or write ends with STOP. However,
the chip requires RESTART after writing the register address.
So the new generic transfer function is perfect for this.
Change-Id: I56d7ebe08f68cb04731c72138d60645ef124f65e
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
If using with shared IRQ, this function will be called by
the shared IRQ driver. So we need to check and bail out
early if the interrupt is not coming from the GPIO
controller.
Change-Id: I4ae925f5fb9a5c32d03a180edc8460e978ec0aac
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Handle only the pins which have been configured to be present on this
controller. Removing an unused #define as well.
Change-Id: I66d3638333f1fcd49b1b4f70a5c9d11dbc538fd0
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
On some platforms (e.g. Galileo), the GPIO controller is on PCI bus,
which shares IRQ with other devices (I2C on Galileo). This patch
adds support for utilizing shared IRQ.
Change-Id: I4b44bae15356e4710d54f0343fed1bd27f35e484
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The polling I2C write function guarantees the write operation
is completed. Given that the initialization routine goes through
I2C write consecutively, we want to make sure each write
has been committed.
Also adds code to configure the I2C controller before transfer.
Change-Id: I2c8888e940edd1cb9fb01f03234a731ac991dfcf
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add I/O port access to MMIO-based GPIO driver, in addition to
the existing direct memory access. This extends the driver,
so that it can address the registers through I/O read/write.
Change-Id: I53c74ad76472ac043764e33bfbb77a2bedc427fe
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
