When running the tests of the async api of uart
on nucleo-l4r5zi we get MPU fault.
The reason is ordering initialization. The uart and dma
drivers are initialized PRE_KERNEL_1 while dmamux is
initialized POST_KERNEL.
Thus, the function device_get_binding fails since the
dmamux device is not ready to be used.
Fixes: #32715.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
Move dmamux_stm32_channels struct from device data to device
configuration and initialize the dmamux channel - dma channel
assignment during build time,
as this association is hardwired in all known series.
The information is taken from dma_offset and dma_requests device tree
properties. The current implementation is valid for series with either
a single or two dma peripherals and a single dmamux peripheral.
Both dmas can independently enabled.
As the driver uses multi-instance DT_INST_DEFINE, also macros for a
second dmamux are are added that should allow easier extension to a
second dmamux instance.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Convert from device_get_binding to DEVICE_DT_GET. In doing this we
no longer need the label in the devicetree node so we remove that.
Removed all __ASSERT_NO_MSG(clk) since we'll get a build error if
DEVICE_DT_GET cant be satisfied, and the clock control api's will
handle reporting if the device_is_ready.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Drivers are using DEVICE_AND_API_INIT which is deprecated so convert
the iproc_pax dma drivers over to using DEVICE_DT_INST_DEFINE and
DEVICE_DT_INST_GET.
Fixes#32153
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
When checking for IRQ flags, we should also check
for IRQ status (IsEnabled ?).
If this is not done we can end up in Half Transfer
interrupt processing while it is not enabled.
Additionaly always use the id translation function
in LL API calls.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add PAX[PCIE<->AXI] DMA driver which supports DMA
transfers between host and target memory over PCIe link.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
In preparation for QSPI DMA mode:
-Add a possibility to override driver by the HAL DMA. In that case
stream is set as busy and no configuration nor treatment is done.
In case of interrupt, flags clearing is let to HAL.
-Treat Half Transfer interrupt prior to Transfer Complete for the
cases were both IRQ are both raised at the time IRQ handler is called
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that we generate a header that extern's all possible devicetree
based device struct we can remove DEVICE_DT_DECLARE and
DEVICE_DT_INST_DECLARE as they aren't needed anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In order to simplify the handling of DMA_STM32_V1/V2 and DMAMUX_STM32
symbols, set them directly based on related compatible status.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2 versions of DMA hardware blocks could be found across stm32 series.
In order to simplify the handling of matching Kconfig symbols,
make this visible in dts files by creating "st,stm32-dma-v1" and
"st,stm32-dma-v2" and set them accordingly in dtsi files.
Duplicate and update related bindings to reflect that new state.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add `get_status` function to dmamux driver api.
This uses the regular dma driver `get_status` function.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
Convert driver(s) to DEVICE_DEFINE instead of DEVICE_AND_API_INIT
so we can deprecate DEVICE_AND_API_INIT in the future.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
It raises an error in case the source data width differs
from the dest data width.
The dma_stm32_width_config function is no more useful: removed.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This new offset value in the dma config is made to
build the table of dma mux_channels with a dmamux.
Range depends on the nb of channels for selected dma instance
Signed-off-by: Francois Ramu <francois.ramu@st.com>
1, Change the allocation of DMA descriptors for the case
when multiple buffers are used for DMA transfer. This was
tested during SPI DMA transfers
2. Add support for the case when source and destination
addresses should not be incremented.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Not possible to use device_get_binding() because we are
currently initializing DMA_1 device, so it is not ready and
device_get_binding() will fail.
Directly use string compare is more efficient.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
The dmamux requires HEAP size definition, so that k_malloc
is valid. The HEAP size config is defined in the common for
any stm32 soc instead of specific to dma Kconfig
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The stm32_dma_disable_stream first checked if the stream was
disabled and if so returned OK. If it wasn't disabled it
tried to disable it and returned -EAGAIN.
The function is used in loops that try to disable the stream
by calling this function and if it fails wait for 1ms and
retry.
Becuase this function the first time (if the stream wasn't
disabled already) fails there is always a 1 ms delay. For
the SPI driver, that has a RX and TX stream, this means
a 2ms delay between the last data and CS going high.
By first trying to disable the stream and than checking
if it succeded most of the time the first call disables
the stream and the 1ms delay isn't needed.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
The general DMA driver doesn't use kmalloc anymore so it doesn't
need a memory pool. The DMAMUX_SMT32 driver still uses kmalloc,
so move the HEAP_MEM_POOL_SIZE config under DMAMUX_STM32.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Use dma_stm32_disable_stream instead of stm32_dma_disable_stream
to check if the disabling of the stream really worked and if
not return an error.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Convert global conversion tables for id-to-stream and slot-to-channel
to functions that use local const static conversion tables.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
- Remove the need for kmalloc
- On hardware that supports it use 1 IRQ handler per stream to
determine the stream ID, so the ISR does not have to loop
over all ID's to see which one is active. On hardware (like
STM32L0 and STM32F0) where up to 7 streams share 3 IRQ's use
the loop to check which stream is active.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Use volatile for flag shared between normal code and ISR to
prevent the compiler from possibly optimizing it away.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
These are all the case that coccinelle cannot find as they are inside
macro declarations.
Fixed via:
git grep -rlz -E "\(struct device \*" |
xargs -0 sed -i 's/(struct device/(const struct device/g'
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Passing the device's config was necessary, and wrapping device inside
it.
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add PL330 dma driver support, this driver
- supports 32 bit memory to memory operation
- supports 36 bit memory to memory operation
under a config flag DMA_64BIT
- supports secure channel
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Add 64bit source_address/dest_address fields support.
This is needed in situation where DMA controller is capable
of handling more than 32bit source and destination addresses.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Add support for the NXP KE1xF SoC to the eDMA driver. The KE1xF supports
m2m DMA transfers from sources 60 to 63.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
