Several drivers checked for the presense and availability of data cache
through Kconfig symbol. This is supported according to the current
documentation, but the symbol DCACHE masks two types of cache devices: arch
and external caches. The latter is present on some Cortex-M33 chips, like
the STM32U5xx. The external dcache is bypassed when accessing internal
SRAM and only used for external memories.
In commit a2dd232410 ("drivers: adc: stm32: dma support") the rationale
for gating dcache for adc_stm32 behind STM32H7X is only hinted at, but
reason seems to be that it was the only SOC the change was tested on. The
SOC configures DCACHE=y so it is most likely safe to swap the SOC gate for
DCACHE.
The DCACHE ifdefs are now hidden inside the shared stm32_buf_in_nocache()
implementation.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Allow STM32 ADC driver to operate with DMA support even when
CONFIG_MEM_ATTR is disabled which happen when CONFIG_ARM_MPU is
intentionally disabled despite the CPU supports MPU.
By the way, remove some #ifdef directive on header files inclusion
that add noise in the header file inclusion section without any
benefit. Also remove inclusion of zephyr/arch/cache.h that is not
needed at all.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
On STM32N6, the register holding the data is 32 bits and DMA must operate
in word transfer to work properly. So we change the type of the buffer in
which we store the ADC data from uint16_t to uint32_t for N6.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
config->base is already defined as ADC_TypeDef so no there is no need to
cast it as such. Remove all occurrences throughout the file.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that clock source and sequencer are defined with strings in device
tree, move the old defines directly in the driver
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that st,adc-sequencer and st,adc_clock-source use a string, update the
ADC driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
fu drv adc update driver with string
Remove specific cases for H7 and U5: group them together and only call a
single function. ADC3 of H72x/H73x and ADC4 of U5 are different from other
ADC of their series, and have dedicated functions in the LL for enabling
DMA, but they're doing the exact same operation as
LL_ADC_REG_SetDataTransferMode.
Incidentally, this change allows H7A/H7B to use the DMA (it seems to have
been missed before).
Last, this change enables the DMA support for F1x ADC.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
STM32F3 and H7 have multiple ADC versions difficult to differentiate.
Use clearer macros to make code more readable.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that the U5 HAL contains the dedicated LDO status function, use it
instead of reading the register directly.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Move all adc driver api structs into an iterable section, this allows us
to verify if an api pointer is located in compatible linker section.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
STM32F1 doesn't have synchronous/asynchronous source clock choice.
The recently added clock check was failing compilation for these series.
This commit removes the check for F1.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add a compile-time check to verify that a domain clock is explicitly
defined if a STM32 ADC is configured to use an asynchronous clock.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add Data Memory Barrier during the extended calibration of STM32U5, as it
is done in STM32Cube HAL, to avoid sporadic errors during calibration that
may result in measures that are offset from real values.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Commit 47187a9ec9 made the `pinctrl` property
of STM32 ADCs optional, to allow usage of internal channels without wasting
GPIO pins. However, the driver was not adapted to support this new usecase.
(The real bug comes from commit 93956b2073,
that transitioned from a custom `stm32_dt_pinctrl_configure` function to
the standard `pinctrl_apply_state`, without accounting for the fact that
the former returns 0 when pinctrl is empty, but the latter returns -ENOENT)
Modify the driver to work even if no `pinctrl` is present on the ADC node.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The STM32H5x adc has a special option register that
needs to be set when using channel 0 on adc1.
fixes: #77618
Signed-off-by: Lars Jeppesen <lje@foss.dk>
For STM32H7, U5 and WBA, check the LDORDY bit of the ADC ISR register
after enabling the internal regulator. This method is safer than the
delay.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Introduce the stm32h7RS serie to the ADC driver,
based on the stm32h7: two ADC 12 resolution
For stm32h7rs ADC calibration, the
LL_ADC_SetCalibrationFactor is not used.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add a blank define for the case where DMA channels are defined in ADC node
of the dts but STM32_ADC_DMA is not enabled. Otherwise compilation fails.
Also fix the way the DMA channel is configured by using a standard DT
macro, otherwise it doesn't work for dma-v2bis DMA types.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Added the STM32G0X SOC series to the list of SOC that need to disable the
ADC while setting the oversampling bits to prevent writing over the
CKMODE bits.
Signed-off-by: Alexandre Poizat <apoizat@kalrayinc.com>
Do not disable the ADC after the end of the measurement to avoid systematic
enabling which is time-consuming in case the configuration is unchanged.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Prevents the system to go in Suspend to RAM low power mode while ADC
measurement is in progress.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For series that have two sampling time common channels, only one was used.
This commit add the support for the second one. The first two different
acquisition time values are used for the sequence and all further values
must match either of them, otherwise generating an error.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Several STM32 variants include both shared IRQs for some ADCs and
separate IRQs for others (for example, STM32G473 has 5 ADCs, ADC1 and
ADC2 share one IRQ while ADC3, ADC4 and ADC5 each have unique
IRQs). The STM32 ADC driver however previously only supported either
separate IRQ lines for each operational ADC in the devicetree or a
single shared IRQ for all operational ADCs in the devicetree which
prevented all ADCs from being usable at the same time when the variant
contained a mix of both shared and separate ADC IRQ lines (only either
all the shared or all the separate and one of the shared might be used
at most for one application).
To allow for all ADCs in an STM32 variant to be usable in a single
application, generate an ISR and initialization function for each
unique IRQn as defined in the devicetree and give the task of
initialization to the first ADC which connects to that particular
IRQ. Each ISR function will generate code to call the ISR for each ADC
associated with that IRQn as was previously done for
CONFIG_ADC_STM32_SHARED_IRQS, allowing an ISR to be shared for the
ADCs sharing an IRQ while simultaneously providing separate ISRs for
each IRQ. Thus, the only information required to have ADCs either
share an ISR or not is provided by the devicetree.
Signed-off-by: Michael R Rosen <mrrosen@alumni.cmu.edu>
When using one of the internal channels (die_temp, vbat, vref) the
channels are enabled in the individual drivers and disabled again
whenever an adc conversion is complete.
This creates a race condition if the ADC is used from multiple threads.
This commit moves the disabling of the channels to the individual
drivers.
Signed-off-by: Brian Juel Folkmann <bju@trackunit.com>
Configure the sw trigger just after calibration
So the conversion can start on regular channel on the
software control bit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds support for more STM32 CPUs that has
a different DMA interface. This was tested only for
the nucleo_l476rg.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Previously the STM32 DMA driver was dependent on a very specific
name for the DMA in the DTS. This hidden requirement has caused
a bit of confusion. This commit changes the driver to instead
always use the first DMA listed in the ADC node's dma property.
Should fix: #65387
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
CONFIG_NOCACHE_MEMORY is a valid way of declaring buffers in
nocache regions. Consider them valid in the STM32 ADC driver
nocache check.
Copied from commit 818aa2d
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 ADC that use common sampling times, there is a check made to
ensure that all channels of a sequence use the same sampling time.
The value was not reset between reads, resulting in error if two
consecutive sequences used different values.
This commit adds a reset of this value once read is done.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove CHANNEL_COUNT limit used to check the channel bitmask.
This value was not applicable on STM32L1 where channel can go up to 31.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
On some STM32 families (such as F4), temperature and Vbat sensor share the
same ADC channel, which can lead to conflict when reading them, and wrong
measurement can follow.
To alleviate this problem, this commit moves the setting of the common
path internal channel to the sensor drivers themselves instead of doing
it in the ADC driver.
The teardown is still done in the ADC driver, systematically, instead of
channel by channel (which has the same result).
By moving this logic in the sensor drivers, the properties temp-channel,
vbat-channel and vref-channel becomes useless and are thus removed.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
