For ADCs that use a common register for sampling times, improve the error
message when the common registers are already set and can't accept a new
value.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
To reset channel preselection register (PCSEL), low-level function
LL_ADC_SetChannelPreselection has been used. This function does not clear
any bit as it uses bitwise OR and can only set the bit. Replace this with
stm32_reg_write() to clear whole register with 0.
Signed-off-by: Marin Jurjević <marinjurjevic@outlook.com>
Channel preselection condition uses bitwise operation on raw
register value to check if channel needs setup. Use BIT(channel_id)
macro to extract relevant bit instead of channel.
Signed-off-by: Marin Jurjević <marinjurjevic@outlook.com>
In streaming mode the application does not supply a buffer in the
adc_sequence; sample data is written into a buffer allocated from the
RTIO mempool inside the ISR. Skip the sequence buffer size validation
in start_read() when CONFIG_ADC_STREAM is enabled, which otherwise
fails with a spurious -ENOMEM "Provided buffer is too small" error.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Change calibration process to handle differential calibration
Configure channel 10 to differential for Nucleo N657X0-Q and
STM32N6570-DK in `adc_api` test
Pin PA10 (Arduino A2) is shared as positive input for channel 11
and negative input for channel 10, allowing to keep default pin
configuration to test single and differential input.
Signed-off-by: Basile GRUNER <basile.gruner@smile.fr>
The LL_ADC_GetChannelSingleDiff function to know whether an ADC channel
is configured as differential or single-ended was not used correctly.
This lead to systematically disabling the ADC to reconfigure it, even if
the configuration was already the correct one.
Instead of returning the mode, LL_ADC_GetChannelSingleDiff returns the
channel if it is configured as differential, or 0 if it is single-ended.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
If the channel setup function is called while an ADC conversion is
on-going, it can lead the system to hang indefinitely. Prevent this by
adding a locking mechanism on the setup function, similar to what is
done for the read function.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
On STM32H5, the bit 0 of the Option register of ADC1 controls the channel 0
switch control. It has to be set if either ADC1 or ADC2 wants to use this
channel. Until now, it was enabled only if ADC1 requested channel 0. This
commit fixes this by setting the option bit if channel 0 is used, with no
consideration of the ADC instance.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
STM32H72x/73x ADC have a PCSEL_RES0 register instead of PCSEL for other
series.
Make a special case to prevent a compilation error.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
To prevent missing calibration when adding new series, add an error
message if no calibration is done.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the new has-injected-support property in the Kconfig instead of
filtering on series directly, and use it also in the driver to return an
error if a specific instance doesn't support injected (this is the case
for STM32U5 where ADC1 and 2 support injected, but not ADC4).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
In order to write into some ADC registers, it is necessary to have no
on-going conversions (either regular, injected, or both). Until now, each
time such a write was needed, the ADC was disabled unconditionally,
stopping any potential on-going conversion.
With the introduction of the injected mode, this could lead to problems
if for example an injected is configured differently than a running
regular one. In that case it would stop the regular conversion. If the
application is waiting the result before starting another one, it will be
stuck waiting forever.
To avoid cases like this, return an error rather than stopping conversion
and disabling the ADC. This reworks many functions to return an error in
case it was not possible to safely disable the ADC.
It stays possible to force an ADC disable even though a conversion is
running, this is useful at init where we don't want this to fail.
This also creates a dedicated function for the preselection register to
avoid duplication.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add injected mode support for STM32 ADC driver. To avoid potential
conflicts when configuring the ADC registers, some settings (like presel)
are moved into the channel_setup function when injected is enabled.
Also configures an ISR when DMA and injected mode are enabled. The reason
is that DMA is not available for injected sequence, so an ISR is still
necessary in this case.
Factorizes the "start_read_xxx" functions to avoid needless duplication
between sync/async and regular/injected mode.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
It is unnecessary since it is never set to continuous (and single is the
default value), and causes issues on STM32F1 by starting conversions out
of turn (setting ADON bit while it is already set, without changing
any other bit in the register start a conversion).
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
If the clock device (i.e., RCC) failed to initialize, we have bigger
problems than trying to call clock_control_{off,on,configure} on it.
Don't bother checking to save some footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
As reported in #101190, running adc_sequence sample on stm32f103c8 with 8
ADC channels causes all subsequent conversions after the first to be one
channel shifted. This is because writing to CR2 with ADON=1 and no other
changes triggers a conversion (which is why the bug happens on all
but the first sequence). Adding this check will ensure that CR2 is only
written when the DMA bit changes.
Signed-off-by: Benedek Kupper <kupper.benedek@gmail.com>
Some internal _CONCAT* macros were used throughout the file. Replace them
with the simple CONCAT macro.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Rework the way to set the STM32 ADC resolution.
Instead of using special macros in device tree, supported resolutions are
now simply listed as an array.
From this array, the driver defines two tables. The first contains the same
values as the array, the second contains the LL macros for each resolution.
When setting the resolution, the driver checks the value with the first
table, then sets it with the second table.
The two tables are defined for each enabled ADC instance so there are no
conflicts if different ADC have different resolutions.
For STM32H7, this changes the internal values used for 14 and 12-bit
resolutions, from 0b101/110 to 0b001/010 respectively, i.e. it uses the
so-called "legacy" resolutions instead of the "power-optimized" ones.
Note that AN5354 indicates: "The optimized modes have better power
consumption figures. The standard modes have better parameters, but
power consumption is not optimized and is comparable to 16-bit mode."
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
set_sequencer() never reports errors and always returns 0.
The error check at the call site is therefore dead code.
Make the function void and drop the unused error handling.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
Remove duplicated #include directives within the same
preprocessor scope across the Zephyr tree.
Duplicates inside different #ifdef branches are preserved
as they may be intentional.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
If several ADCs are used and share a common clock property (for example
ADC1/2 prescaler value on STM32U5), none of them should be enabled when
the clock is set.
To that end, make sure to disable ADC at the end of the initialization,
it will be enabled later when necessary anyway.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The burst length unit is bytes, not number of transfers. This had not been
an issue since the DMA driver historically ignored the values, but has now
become one since they are used and (most importantly for us) validated.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Use STM32_CLOCK_INFO(), STM32_DT_INST_CLOCK_INFO(),
STM32_CLOCK_INFO_BY_NAME() and STM32_DT_INST_CLOCK_INFO_BY_NAME()
helper macros in STM32 drivers.
Using these macros ensure the clock division factor is properly
populated according to DT information. Prior these changes some
drivers only got the bus and bits position information and missed
the clock division information which is fine only when this division
factor information is 0.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Some series like F1, F3, N6 and U3 use an ADC prescaler defined in the RCC.
Instead of adding specific properties in the RCC driver, use the secondary
clock system to configure the prescaler.
The ADC driver now configures the clocks depending on their presence and
their name. Three clocks can be defined:
- the register clock (mandatory for all series)
- the kernel clock (depends on series)
- the prescaler value (depends on series)
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 drivers and SoC, replace the MODIFY_REG macro (defined in
the STM32 HAL) by stm32_reg_modify_bits defined in Zephyr.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 drivers, replace the SET_BIT macro (defined in
the STM32 HAL) by stm32_reg_set_bits defined in Zephyr.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
In STM32 ADC binding, rename the possible values of the sequencer and
oversampler properties to use lowercase string, similar to the internal
regulator.
Adapts the driver and the dtsi with the new values.
Fixes a macro issue in the driver. Since the value from the dtsi didn't
start with internal_regulator_, the reconstruction of the defines by
the macro ANY_ADC_INTERNAL_REGULATOR_TYPE_IS was missing this prefix and
the comparison failed. Add a new argument to the IS_EQ_STRING_PROP to be
able to insert such a prefix.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Disabling the internal regulator is immediate so there is no need to check
the state of the Enable bit in the register.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the new differential support property instead of relying on the series
name to determine if the ADC supports differential input channels.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the new channel preselection property instead of relying on the series
name to determine if the ADC channels need to be preselecting.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the new deep powerdown property instead of relying on the series name
to determine if the ADC needs to be be put out or into deep powerdown mode.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the new internal regulator property instead of relying on series name
to determine if the regulator should be enabled, and how to check that it
is ready.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For managing the CCRDY flag, rely on the presence of the LL constant
LL_ADC_FLAG_CCRDY rather than a list of series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove address-of operator ('&') when assigning `adc_xxx_init`
function pointer in `DEVICE_DT_INST_DEFINE` and `DEVICE_DT_DEFINE` macro.
This change aims to maintain consistency among the drivers in
`drivers/adc`, ensuring that all function pointer assignments
follow the same pattern.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add an explicit check to ensure that the acquisition_time
parameter is encoded with the ADC_ACQ_TIME macro and uses
the TICKS unit, as required by the API.
If the unit is not correct, log an error and return -EINVAL.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
The stm32u3x header files defines LL_ADC_SINGLE_ENDED but not
LL_ADC_DIFFERENTIAL as the device doesn't support differential mode. The
driver only checked for LL_ADC_SINGLE_ENDED and assumed that when that was
defined, LL_ADC_DIFFERENTIAL would also be defined.
Check for both when figuring out which calibration type will be required.
Signed-off-by: Keith Packard <keithp@keithp.com>
Differential mode support consists of:
- If differential mode is supported by the underlying hardware AND at
least one differential channel is enabled in the devicetree for this
ADC instance, then perform a differential mode calibration in addition
to the usual single ended calibration during initialisation.
- Set channels to the appropriate differential or single ended mode
during channel setup.
Currently the N6 series is not supported even though the underlying
hardware supports differential mode, due to complications in the
calibration procedure.
Signed-off-by: Matt Rodgers <mrodgers@witekio.com>
Co-authored-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Several drivers checked for the presense and availability of data cache
through Kconfig symbol. This is supported according to the current
documentation, but the symbol DCACHE masks two types of cache devices: arch
and external caches. The latter is present on some Cortex-M33 chips, like
the STM32U5xx. The external dcache is bypassed when accessing internal
SRAM and only used for external memories.
In commit a2dd232410 ("drivers: adc: stm32: dma support") the rationale
for gating dcache for adc_stm32 behind STM32H7X is only hinted at, but
reason seems to be that it was the only SOC the change was tested on. The
SOC configures DCACHE=y so it is most likely safe to swap the SOC gate for
DCACHE.
The DCACHE ifdefs are now hidden inside the shared stm32_buf_in_nocache()
implementation.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Allow STM32 ADC driver to operate with DMA support even when
CONFIG_MEM_ATTR is disabled which happen when CONFIG_ARM_MPU is
intentionally disabled despite the CPU supports MPU.
By the way, remove some #ifdef directive on header files inclusion
that add noise in the header file inclusion section without any
benefit. Also remove inclusion of zephyr/arch/cache.h that is not
needed at all.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
On STM32N6, the register holding the data is 32 bits and DMA must operate
in word transfer to work properly. So we change the type of the buffer in
which we store the ADC data from uint16_t to uint32_t for N6.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
config->base is already defined as ADC_TypeDef so no there is no need to
cast it as such. Remove all occurrences throughout the file.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
