Some series like F1, F3, N6 and U3 use an ADC prescaler defined in the RCC.
Instead of adding specific properties in the RCC driver, use the secondary
clock system to configure the prescaler.
The ADC driver now configures the clocks depending on their presence and
their name. Three clocks can be defined:
- the register clock (mandatory for all series)
- the kernel clock (depends on series)
- the prescaler value (depends on series)
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 drivers and SoC, replace the MODIFY_REG macro (defined in
the STM32 HAL) by stm32_reg_modify_bits defined in Zephyr.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 drivers, replace the SET_BIT macro (defined in
the STM32 HAL) by stm32_reg_set_bits defined in Zephyr.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
In STM32 ADC binding, rename the possible values of the sequencer and
oversampler properties to use lowercase string, similar to the internal
regulator.
Adapts the driver and the dtsi with the new values.
Fixes a macro issue in the driver. Since the value from the dtsi didn't
start with internal_regulator_, the reconstruction of the defines by
the macro ANY_ADC_INTERNAL_REGULATOR_TYPE_IS was missing this prefix and
the comparison failed. Add a new argument to the IS_EQ_STRING_PROP to be
able to insert such a prefix.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Disabling the internal regulator is immediate so there is no need to check
the state of the Enable bit in the register.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the new differential support property instead of relying on the series
name to determine if the ADC supports differential input channels.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the new channel preselection property instead of relying on the series
name to determine if the ADC channels need to be preselecting.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the new deep powerdown property instead of relying on the series name
to determine if the ADC needs to be be put out or into deep powerdown mode.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the new internal regulator property instead of relying on series name
to determine if the regulator should be enabled, and how to check that it
is ready.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For managing the CCRDY flag, rely on the presence of the LL constant
LL_ADC_FLAG_CCRDY rather than a list of series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove address-of operator ('&') when assigning `adc_xxx_init`
function pointer in `DEVICE_DT_INST_DEFINE` and `DEVICE_DT_DEFINE` macro.
This change aims to maintain consistency among the drivers in
`drivers/adc`, ensuring that all function pointer assignments
follow the same pattern.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add an explicit check to ensure that the acquisition_time
parameter is encoded with the ADC_ACQ_TIME macro and uses
the TICKS unit, as required by the API.
If the unit is not correct, log an error and return -EINVAL.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
The stm32u3x header files defines LL_ADC_SINGLE_ENDED but not
LL_ADC_DIFFERENTIAL as the device doesn't support differential mode. The
driver only checked for LL_ADC_SINGLE_ENDED and assumed that when that was
defined, LL_ADC_DIFFERENTIAL would also be defined.
Check for both when figuring out which calibration type will be required.
Signed-off-by: Keith Packard <keithp@keithp.com>
Differential mode support consists of:
- If differential mode is supported by the underlying hardware AND at
least one differential channel is enabled in the devicetree for this
ADC instance, then perform a differential mode calibration in addition
to the usual single ended calibration during initialisation.
- Set channels to the appropriate differential or single ended mode
during channel setup.
Currently the N6 series is not supported even though the underlying
hardware supports differential mode, due to complications in the
calibration procedure.
Signed-off-by: Matt Rodgers <mrodgers@witekio.com>
Co-authored-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Several drivers checked for the presense and availability of data cache
through Kconfig symbol. This is supported according to the current
documentation, but the symbol DCACHE masks two types of cache devices: arch
and external caches. The latter is present on some Cortex-M33 chips, like
the STM32U5xx. The external dcache is bypassed when accessing internal
SRAM and only used for external memories.
In commit a2dd232410 ("drivers: adc: stm32: dma support") the rationale
for gating dcache for adc_stm32 behind STM32H7X is only hinted at, but
reason seems to be that it was the only SOC the change was tested on. The
SOC configures DCACHE=y so it is most likely safe to swap the SOC gate for
DCACHE.
The DCACHE ifdefs are now hidden inside the shared stm32_buf_in_nocache()
implementation.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Allow STM32 ADC driver to operate with DMA support even when
CONFIG_MEM_ATTR is disabled which happen when CONFIG_ARM_MPU is
intentionally disabled despite the CPU supports MPU.
By the way, remove some #ifdef directive on header files inclusion
that add noise in the header file inclusion section without any
benefit. Also remove inclusion of zephyr/arch/cache.h that is not
needed at all.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
On STM32N6, the register holding the data is 32 bits and DMA must operate
in word transfer to work properly. So we change the type of the buffer in
which we store the ADC data from uint16_t to uint32_t for N6.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
config->base is already defined as ADC_TypeDef so no there is no need to
cast it as such. Remove all occurrences throughout the file.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that clock source and sequencer are defined with strings in device
tree, move the old defines directly in the driver
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that st,adc-sequencer and st,adc_clock-source use a string, update the
ADC driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
fu drv adc update driver with string
Remove specific cases for H7 and U5: group them together and only call a
single function. ADC3 of H72x/H73x and ADC4 of U5 are different from other
ADC of their series, and have dedicated functions in the LL for enabling
DMA, but they're doing the exact same operation as
LL_ADC_REG_SetDataTransferMode.
Incidentally, this change allows H7A/H7B to use the DMA (it seems to have
been missed before).
Last, this change enables the DMA support for F1x ADC.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
STM32F3 and H7 have multiple ADC versions difficult to differentiate.
Use clearer macros to make code more readable.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that the U5 HAL contains the dedicated LDO status function, use it
instead of reading the register directly.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Move all adc driver api structs into an iterable section, this allows us
to verify if an api pointer is located in compatible linker section.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
STM32F1 doesn't have synchronous/asynchronous source clock choice.
The recently added clock check was failing compilation for these series.
This commit removes the check for F1.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add a compile-time check to verify that a domain clock is explicitly
defined if a STM32 ADC is configured to use an asynchronous clock.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add Data Memory Barrier during the extended calibration of STM32U5, as it
is done in STM32Cube HAL, to avoid sporadic errors during calibration that
may result in measures that are offset from real values.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Commit 47187a9ec9 made the `pinctrl` property
of STM32 ADCs optional, to allow usage of internal channels without wasting
GPIO pins. However, the driver was not adapted to support this new usecase.
(The real bug comes from commit 93956b2073,
that transitioned from a custom `stm32_dt_pinctrl_configure` function to
the standard `pinctrl_apply_state`, without accounting for the fact that
the former returns 0 when pinctrl is empty, but the latter returns -ENOENT)
Modify the driver to work even if no `pinctrl` is present on the ADC node.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The STM32H5x adc has a special option register that
needs to be set when using channel 0 on adc1.
fixes: #77618
Signed-off-by: Lars Jeppesen <lje@foss.dk>
For STM32H7, U5 and WBA, check the LDORDY bit of the ADC ISR register
after enabling the internal regulator. This method is safer than the
delay.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Introduce the stm32h7RS serie to the ADC driver,
based on the stm32h7: two ADC 12 resolution
For stm32h7rs ADC calibration, the
LL_ADC_SetCalibrationFactor is not used.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add a blank define for the case where DMA channels are defined in ADC node
of the dts but STM32_ADC_DMA is not enabled. Otherwise compilation fails.
Also fix the way the DMA channel is configured by using a standard DT
macro, otherwise it doesn't work for dma-v2bis DMA types.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Added the STM32G0X SOC series to the list of SOC that need to disable the
ADC while setting the oversampling bits to prevent writing over the
CKMODE bits.
Signed-off-by: Alexandre Poizat <apoizat@kalrayinc.com>
Do not disable the ADC after the end of the measurement to avoid systematic
enabling which is time-consuming in case the configuration is unchanged.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Prevents the system to go in Suspend to RAM low power mode while ADC
measurement is in progress.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For series that have two sampling time common channels, only one was used.
This commit add the support for the second one. The first two different
acquisition time values are used for the sequence and all further values
must match either of them, otherwise generating an error.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
