Compiler capability probes go through try_compile(), which only sees
CMAKE_REQUIRED_FLAGS; the target flags collected in TOOLCHAIN_C_FLAGS are
applied as target properties and never reach it. CMake propagates
'--target=<triple>' on its own, but the triples set by the LLVM toolchain
only pin the architecture profile, so probes run against clang's default
CPU for that triple: cortex-m3 soft-float for armv7m-none-eabi, generic
soft-float for armv8m.main-none-eabi, and rv32imac/ilp32 for
riscv32-unknown-elf regardless of the configured extensions.
Pass the architecture flags that the triple does not carry, so flag
support is decided for the ISA actually being built. This also makes the
toolchain capability cache key, which is derived from the compiler
signature and CMAKE_REQUIRED_FLAGS, distinguish targets that share the
same clang binary.
Assisted-by: Claude:opus-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
CMake stopped adding -mcpu itself once CMP0123 became NEW, and Zephyr
only passes it through TOOLCHAIN_C_FLAGS, which does not reach
try_compile. Compiler capability probes were therefore evaluated
against armclang's default CPU rather than the one being built for.
Add -mcpu to CMAKE_REQUIRED_FLAGS so probe results match the target.
Assisted-by: Claude:opus-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
GCC 11+ defaults to DWARF v5, and -gdwarf-4 was forced only because
older pyelftools could not parse it. pyelftools has supported DWARF v5
since 0.27, and Zephyr now requires pyelftools>=0.29 (with CI pinned to
0.33), so the workaround is no longer needed. Remove the forced
-gdwarf-4 from both the compiler and linker flags to let GCC emit its
default DWARF version.
Assisted-by: Claude:opus-4.8
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
add -Wno-parentheses-equality, so
clang doesn't complain about redundant
parenthesis, like it does when K_TIMEOUT_EQ()
is directly used in a if.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
commit 6612580d9e introduced PRECISION_TOKEN to pass -mfpu=fpv5-sp-d16
to GCC for Cortex-M55 SoCs with a single-precision-only FPU.
commit 570ef09d0f reverted FPU_FOR_cortex-m55 back to "auto" in the
shared gcc-m-fpu.cmake to fix a clang regression (clang treats an
explicit -mfpu= as a capability override, which silently disables
mve.fp). However, GCC derives MVE capability from -mcpu alone and is
not affected by -mfpu=fpv5-sp-d16, so the revert was too broad: GCC
now also sees "auto" and assumes the full double-precision default
implied by -mcpu=cortex-m55, ignoring the SoC's actual hardware.
Fix this in the GCC-specific target_arm.cmake: when GCC_M_FPU is
"auto" and CPU_HAS_FPU_DOUBLE_PRECISION is not set, pass
-mfpu=fpv5-sp-d16 explicitly. The clang and armclang paths already
skip -mfpu= for "auto" (commits 570ef09d0f and f30235f56a
respectively) and are unaffected.
Co-Authored-By: Claude <noreply@anthropic.com>
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Add the XC32 toolchain configuration files needed for Zephyr
to detect and use the Microchip compiler toolchain with the
expected compile/link defaults.
Signed-off-by: Ashish Mahanth <ashish.mahanth@microchip.com>
OpenRISC runs code from RAM (non-XIP), so the single LOAD segment
legitimately needs RWX permissions. Add --no-warn-rwx-segments to
prevent ld >= 2.39 from turning this into an error under
--fatal-warnings.
Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>
gcov belongs in target.cmake and not generic.cmake.
generic.cmake are for generic tools that are needed during build system
generation, before the arch is known, for example for Kconfig
pre-processing.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Lightweight write sanitizer for sys_heap. Uses
-fsanitize=kernel-address compiler instrumentation combined with a
per-heap shadow bitarray (one bit per granule) to detect buffer
overflows, underflows, and use-after-free on write accesses.
Ships its own lightweight sanitizer runtime (__asan_store* callbacks);
does not depend on an external ASAN library and supports debugging on
real embedded targets.
Instrumentation is opt-in per CMake target via
zephyr_target_enable_heap_kasan(), or per directory via
zephyr_heap_kasan_enable_directory(). Only writes are checked
(-asan-instrument-reads=0). Bulk-write library calls (memset,
memcpy, str*, printf family) are redirected to checked wrappers at
compile time via -Dfoo=__asan_foo, requiring no source changes in
application code.
Heap tracking is likewise opt-in: register each heap with
SYS_HEAP_KASAN_ENABLE() / K_HEAP_KASAN_ENABLE(), or enable
CONFIG_SYS_HEAP_KASAN_MALLOC / CONFIG_SYS_HEAP_KASAN_SYSTEM for the
common libc malloc and kernel system heaps.
Usage:
CONFIG_SYS_HEAP_KASAN=y
CONFIG_SYS_HEAP_KASAN_MALLOC=y # auto-track malloc/free
CONFIG_SYS_HEAP_KASAN_SYSTEM=y # auto-track k_malloc/k_free
# Instrument all sources of <target> (CMakeLists.txt)
zephyr_target_enable_heap_kasan(app)
# Or instrument sources under <dir>
zephyr_heap_kasan_enable_directory(src/mymodule)
/* Opt-in tracking for a custom heap */
K_HEAP_DEFINE(my_heap, 4096);
K_HEAP_KASAN_ENABLE(my_heap, 4096);
Signed-off-by: Jinming Zhao <jinmzhao@qti.qualcomm.com>
Add RISCV_ISA_EXT_ZK (Scalar Cryptography) and RISCV_ISA_EXT_ZKS
(ShangMi Suite) Kconfig options, and append them to the GCC march
flag when enabled.
Signed-off-by: Liu Qian <liuqian.andy@picoheart.com>
As a part of the AIA specification two new extensions were introduced:
Smaia (Supervisor Machine AIA) and Ssaia (Supervisor Software AIA).
Support is added for these 2 extensions
Signed-off-by: Omar Naffaa <onaffaa@qti.qualcomm.com>
Avoid exporting the ARMClang builtin header path ahead of
libc++ for C++ builds, and restrict
_AEABI_PORTABILITY_LEVEL=1 to C and ASM.
This restores the expected C++ standard library include
behavior and avoids applying C-only AEABI portability
handling to libc++.
Assisted-by: GitHub Copilot:GPT-5.4 [apply_patch] [run_in_terminal]
Signed-off-by: Evan Chen <bugena123@gmail.com>
The -mno-global-merge flag is not recognized by Clang. Since GCC also
sets this property to an empty string, update Clang to match for
cross-platform compatibility. This fixes RISC-V builds with Clang.
Fixes build error on qemu_riscv32e with LLVM:
clang: error: argument unused during compilation: '-mno-global-merge'
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Clang doesn't support -mstack-protector-guard flags that are used by
GCC. These flags are particularly problematic on RISC-V where they
cause compilation failures.
Override the security_canaries properties in Clang to only include the
base -fstack-protector variants, removing the unsupported
-mstack-protector-guard flags inherited from GCC.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Clang does not support the GCC-specific -flto=auto and -flto=1
flag forms, causing build failures when LTO is enabled with the
LLVM toolchain:
clang: error: unsupported argument '1' to option '-flto='
Override optimization_lto and optimization_lto_st in the Clang
compiler flags to use the Clang-supported equivalents:
- optimization_lto: -flto=thin (parallel, replaces -flto=auto)
- optimization_lto_st: -flto=full (single-threaded, replaces -flto=1)
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Define ARM-specific LLEXT compile flags for the clang toolchain
configuration to match GCC behavior.
This adds long-call code generation for extension objects and disables
unwind table emission in llext builds.
Also strip ARM unwind metadata sections from packaged .llext files so
the loader does not encounter relocations against non-loaded unwind
sections (.ARM.exidx/.ARM.extab and related rel sections).
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Two related problems caused clang/LLVM to disable MVE floating-point
(-mve.fp) when targeting Cortex-M55:
1. cmake/gcc-m-fpu.cmake set FPU_FOR_cortex-m55 to fpv5-sp-d16 (commit
6612580d9e) to allow precision selection via PRECISION_TOKEN. For
GCC this is harmless because GCC derives MVE capability from -march.
For clang, -mfpu=fpv5-sp-d16 explicitly overrides the CPU's default
FPU capabilities, which disables mve.fp:
clang -mcpu=cortex-m55 -mfpu=fpv5-sp-d16 -> +nomve.fp (wrong)
clang -mcpu=cortex-m55 -> +mve.fp (correct)
restore FPU_FOR_cortex-m55 to "auto". The +nomve.fp, +nomve and
+nodsp variants keep fpv5-sp-d16 because they explicitly restrict FPU
capabilities.
2. cmake/compiler/clang/target_arm.cmake unconditionally passed
-mfpu=${GCC_M_FPU} when CONFIG_FPU is set, with no guard for "auto".
The equivalent armclang fix was applied in commit f30235f56a but was
never ported to the standalone clang toolchain path.
add the same NOT "auto" guard as armclang/target.cmake.
Fixes#109009
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move `string(GENEX_STRIP ...)` before the loop.
We want to strip generator expressions from INTERFACE_COMPILE_OPTIONS.
This needs to be done before looping the list so that a compile option
list like this: `--arg1;$<1:--genarg1;--genarg2>;--arg2` are correctly
processed as a list of
- --arg1
- --arg2
and not an invalid list of
- --arg1
- $<1:--genarg1
- --genarg2>
- --arg2
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Zephyr computes the runtime lib via --print-libgcc-file-name, but does
not pass the C++ compile flags -fno-exceptions and -fno-rtti causing
the probe to always select the wrong c++ rt.
Signed-off-by: Kenth Eriksson <kenth.eriksson@nokia.com>
This change enables per thread stack canary for RISC-V.
RISC-V GCC accesses the stack canary via a fixed offset from the
thread pointer (tp) when -mstack-protector-guard=tls is used. The
compiler emits code equivalent to:
lw t0, 0(tp) # load canary from tp+0
Additionally, tp is zeroed in arch_kernel_init() when TLS is enabled,
which means any C function called before thread setup completes (such
as z_early_rand_get or data_copy_xip_relocation) would fault trying
to access the canary.
Introduce STACK_CANARIES_TLS_PREPEND, which places the
.stack_chk.guard section at offset 0 of the TLS block, before .tdata
and .tbss. The compiler flags -mstack-protector-guard-reg=tp and
-mstack-protector-guard-offset=0 are passed so GCC generates the
correct canary access.
With STACK_CANARIES_TLS_PREPEND the per-thread TLS block layout is:
tp --> +------------------+ offset 0
| .stack_chk.guard | (__stack_chk_guard)
+------------------+
| .tdata | (initialized TLS data)
+------------------+
| .tbss | (zero-initialized TLS data)
+------------------+
The RISC-V reset path is extended to initialize tp before any C code
runs by allocating a TLS area on the boot stack and calling
arch_riscv_early_tls_stack_update(). Early boot functions that run
before tp is set up (z_early_rand_get, data_copy_xip_relocation) are
marked FUNC_NO_STACK_PROTECTOR to avoid canary access before tp is
valid.
Signed-off-by: Mayur Salve <msalve@qti.qualcomm.com>
Add new implementations for entropy driver and random subsystem
based on ARM64 RNDRRS and RNDR instructions.
Signed-off-by: Christoph Busold <cbusold@qti.qualcomm.com>
The iar toolchain fails to build after the update to the
1.0.0 Zephyr SDK. The path to the gnu toolchains
was updated to '${ZEPHYR_SDK_INSTALL_DIR}/gnu/'
in order to be compatible with the 1.0.0 SDK.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
ZephyrSDK v1.0.0 is updated to support RXv2 and RXv3 instruction
this update the gcc cmake configuration for RX build on Zephyr SDK
for RXv2 and RXv3 MCU
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Override the GCC-specific `-Wno-volatile` flag specified by GCC
`compiler_flags.cmake` with the Clang-equivalent
`-Wno-deprecated-volatile`.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Compiler-generated FLIX instructions are currently disabled for LLEXT due
to a historic issue with LLEXT feature that appears to be already
resolved. However, another issue with FLIX is now being investigated.
The latter issue is not related to LLEXT but userspace feature.
To mitigate impact of global complier settings, this change adds a kconfig
choice for controlling FLIX generation independently for LLEXT modules.
Signed-off-by: Wojciech Jablonski <wojciech.jablonski@intel.com>
Add a new compiler property warning_no_misleading_indentation to allow
disabling misleading indentation warnings. This is implemented for GCC
with the -Wno-misleading-indentation flag.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Adds fixes for build and runtime issues using MWDT:
* Rename sections for llext_memblk.c buffers as MWDT cannot initialize
sys_mem_blocks struct with buffer address when the section name of
sys_mem_blocks struct (its variable name) is identical to the
buffer's section name
* Adds --no-check-sections flag for MWDT on final stages of
linking. Unlike other toolchains, MWDT's default behavior is to
strictly check and fail on section overlap. Using SLIDs requires
overlap; see llext-sections.ld
* Modifies inspect test case's ifdef around rodata sections, as
not all Harvard platforms using MWDT have .rodata_in_data sections -
their creation is triggered by passing the -Hccm flag to CCAC.
As an example, nsim/nsim_em doesn't have them and nsim/nsim_vpx5 does
* Removes -Hccm flag when building with CONFIG_LLEXT_RODATA_NO_RELOC
as it causes CCAC to mark the custom section llext.rodata.noreloc
writable (SHF_WRITE) though it has only read-only data, making it
impossible for for LLEXT to recognize it and put it in the
appropriate region; see llext_load.c's llext_map_sections
* Adds name to unnamed first argument of threads_objects_test_setup,
removing warning about omitting parameter names being a
C2x extension
Also fixes a build warning for GCC about pointer arithmetic in
the INSTR_FETCHABLE macro.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Enable the ARM_PACBTI Kconfig choice for ARM64 architectures (ARMV8_A
and ARMV9_A) in addition to the existing ARM32 ARMV8_1_M_MAINLINE
support. Add the corresponding -mbranch-protection compiler flags to
both GCC and Clang target files for ARM64.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This adds the compiler flag to instruct xt-clang not to generate
FLIX (Flexible Length Instruction Xtensions) instructions, where
multiple instructions can be fused into one instruction. FLIX
can provide performance and code size advantages.
When userspace is enabled, FLIX may reorder memory access
where memory is accessed before code determines whether
we should perform that memory access. For example,
when guarding memory access via k_is_user_context(), and
some kernel variables can only be accessed via kernel mode,
FLIX may reorder memory access such that these variables are
accessed before k_is_user_context(). This results in access
violation. This turns off FLIX generation by default and
lets the application developers to decide whether to enable
FLIX generation.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds to compiler flags template on instructing the compiler
on whether to generate VLIW instructions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
seperate fpu mabi and march part, also use
the extention for the march part to make it
easier to add Zfinx and Zdinx later.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Introduce the missing flag to compile code with Zbkb extension,
which has already been supported by the GCC 12 in current SDK.
Signed-off-by: Andy Lin <andylinpersonal@gmail.com>
When building for ARMv9-A platforms with CONFIG_ARM64_SVE disabled,
compilers still emit SVE instructions because ARMv9-A includes SVE
by default in the architecture specification.
Add explicit +nosve flag to -march when CONFIG_ARMV9_A=y but
CONFIG_ARM64_SVE=n to prevent SVE instruction emission. This ensures
the compiler respects the SVE configuration and only emits SVE
instructions when explicitly enabled.
Applied to both GCC and Clang/LLVM toolchains.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
As described in this issue:
https://github.com/zephyrproject-rtos/sdk-ng/issues/1038
`-flto=auto` fails on some (slower) Windows machines due to an issue with
the Zephyr SDK's GCC toolchain for Windows.
In order to allow users to work around this issue, introduce a new
CONFIG_LTO_SINGLE_THREADED option that switches to `-flto=1`, which
enforces a single thread when processing LTO.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This commit fixes bug #95402. When the GNU toolchain is installed
in its default path the library include dir will contain spaces.
By encasulating the library path in quotes the linker works again.
Signed-off-by: Rico van Dongen <rdongen@ziggo.nl>
Implement Scalable Vector Extension (SVE) context switching support,
enabling threads to use SVE and SVE2 instructions with lazy context
preservation across task switches.
The implementation is incremental: if only FPU instructions are used
then only the NEON access is granted and preserved to minimize context
switching overhead. If SVE is used then the NEON context is upgraded to
SVE and then full SVE access is granted and preserved from that point
onwards.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add ARMv9-A architecture support with Cortex-A510 CPU as the default
processor for generic ARMv9-A targets.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add arcmwdt RISC-V core/ISA mapping in target_riscv.cmake to
automatically derive compiler flags from Kconfig settings.
- Select series core flag from SoC Kconfig: -av5rmx/-av5rhx
- Map RISC-V Kconfig to ccac -Z flags (M/A/C/Zicsr/Zifencei/Zicntr)
- Handle compressed logic correctly: -Zc or individual Zc* sub-extensions
- Add F/D and compressed FPU (-Zf/-Zd, -Zcf/-Zcd)
- Add -Zmmul when M is not selected and ZMMUL is enabled
- Use OPTIONAL include to allow for arch-specific target files
Keep early compiler checks stable by not pushing -Z flags into
CMAKE_REQUIRED_FLAGS.
Co-authored-by: Torsten Tejlmand Rasmussen <torsten.rasmussen@nordicsemi.no>
Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
Signed-off-by: Afonso Oliveira <afonso.oliveira707@gmail.com>
Signed-off-by: Torsten Tejlmand Rasmussen <torsten.rasmussen@nordicsemi.no>
