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5896 commits

Author SHA1 Message Date
Benjamin Walsh
b12a8e0914 kernel: introduce single-threaded kernel
For very constrained systems, like bootloaders.

Only the main thread is available, so a main() function must be
provided. Kernel objects where pending is in play will not behave as
expected, since the main thread cannot pend, it being the only thread in
the system. Usage of objects should be limited to using K_NO_WAIT as the
timeout parameter, effectively polling on the object.

Change-Id: Iae0261daa98bff388dc482797cde69f94e2e95cc
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 16:17:39 -05:00
Benjamin Walsh
48db0b3443 arch/all: simpler _SysFatalErrorHandler()
- does not pull in printk(), for potential footprint gain
- does not pull in k_thread_abort(), for single-threaded systems

Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Change-Id: Ibc6a198b81a6cd73117d1e85aa05b92a4501a34d
2016-12-15 16:17:39 -05:00
Benjamin Walsh
8e4a534ea1 kernel: enable and optimize coop-only configurations
Some kernel operations, like scheduler locking can be optmized out,
since coop threads lock the scheduler by their very nature. Also, the
interrupt exit path for all architecture does not have to do any
rescheduling, again by the nature of non-preemptible threads.

Change-Id: I270e926df3ce46e11d77270330f2f4b463971763
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 16:17:38 -05:00
Benjamin Walsh
c3a2bbba16 kernel: add k_cpu_idle/k_cpu_atomic_idle()
nano_cpu_idle/nano_cpu_atomic_idle were not ported to the unified
kernel, and only the old APIs were available. There was no real impact
since, in the unified kernel, only the idle thread should really be
doing power management. However, with a single-threaded kernel, these
functions can be useful again.

The kernel internals now make use of these APIs instead of the legacy
ones.

Change-Id: Ie8a6396ba378d3ddda27b8dd32fa4711bf53eb36
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 16:17:38 -05:00
Benjamin Walsh
88b3691415 kernel/arch: enhance the "ready thread" cache
The way the ready thread cache was implemented caused it to not always
be "hot", i.e. there could be some misses, which happened when the
cached thread was taken out of the ready queue. When that happened, it
was not replaced immediately, since doing so could mean that the
replacement might not run because the flow could be interrupted and
another thread could take its place. This was the more conservative
approach that insured that moving a thread to the cache would never be
wasted.

However, this caused two problems:

1. The cache could not be refilled until another thread context-switched
in, since there was no thread in the cache to compare priorities
against.

2. Interrupt exit code would always have to call into C to find what
thread to run when the current thread was not coop and did not have the
scheduler locked. Furthermore, it was possible for this code path to
encounter a cold cache and then it had to find out what thread to run
the long way.

To fix this, filling the cache is now more aggressive, i.e. the next
thread to put in the cache is found even in the case the current cached
thread is context-switched out. This ensures the interrupt exit code is
much faster on the slow path. In addition, since finding the next thread
to run is now always "get it from the cache", which is a simple fetch
from memory (_kernel.ready_q.cache), there is no need to call the more
complex C code.

On the ARM FRDM K64F board, this improvement is seen:

Before:

1- Measure time to switch from ISR back to interrupted task

   switching time is 215 tcs = 1791 nsec

2- Measure time from ISR to executing a different task (rescheduled)

   switch time is 315 tcs = 2625 nsec

After:

1- Measure time to switch from ISR back to interrupted task

   switching time is 130 tcs = 1083 nsec

2- Measure time from ISR to executing a different task (rescheduled)

   switch time is 225 tcs = 1875 nsec

These are the most dramatic improvements, but most of the numbers
generated by the latency_measure test are improved.

Fixes ZEP-1401.

Change-Id: I2eaac147048b1ec71a93bd0a285e743a39533973
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 15:50:02 -05:00
Benjamin Walsh
e6ebe3a8b4 arm: relinquish one IRQ priority reserved by kernel
The Cortex-M3/4 kernel was reserving priorities 0 and 1 for itself, but
was not registering any exception on priority 0. Only reserve priority 0
and use it for SVC and fault exceptions instead of priority 1.

Change-Id: Iff2405e27fd4bed4e49ab90ec2ae984f2c0a83a6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 15:57:10 +00:00
Benjamin Walsh
c016252108 arm: add CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS kconfig flag
Cortex-M0/M0+ do not have other faults than the hard fault at priority
-1, so they do not need to reserve a priority to allow exceptions to
trigger during handling of ISRs.

Change-Id: I479e439f7bcac70b4b2b787bcd744a4c65437e80
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 15:57:09 +00:00
Benjamin Walsh
f5d0cbe8ad arm: move IRQ_PRIORITY_OFFSET to header file, rename to _IRQ_PRIO_OFFSET
This allows using it in _EXC_PRIO() instead of hardcoding 2 and 3.

Change-Id: I3549be54602643e06823ba63beb6a6992f39f776
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 15:57:08 +00:00
Benjamin Walsh
194a2e3a12 arm: add CPU_CORTEX_M_HAS_BASEPRI kconfig flag
Use it to flag which CPUs can do zero latency interrupts, which depend
on being able to lock up to a specific interrupt priority.

Change-Id: I09f71366ea1d05486e38c513a09abc270884879f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 15:57:07 +00:00
Julien Delayen
176d184fb8 power: Add ARC core suspend and resume support
When going into DEEP_SLEEP mode, the ARC core now saves
its context. This includes:
- All core registers
- Stack pointer
- Program counter (restored by jumping to the restore code)

The arc reset code now checks if the GPS0 bit 2 is set.
This is similar to the behavior of the x86 core done by
the QMSI bootloader which is setting GPS0 bit 1 in order
to call the restore path instead of cold boot path.

The sample has been adapted in order to support the ARC.

Jira: ZEP-1222

Change-Id: I375f03b16b8a5fd1f07ead55cf7e4947d6290c9f
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
2016-12-15 12:49:33 +00:00
Julien Delayen
cd8504cc9c arcv2_irq: Add power management suspend/resume
In order to resume the ARC from deep sleep,
the interrupts need to be restored.

The FIRQ stack needs to be saved and restored
when performing sleep operations.

During early initialization, the sp in the 2nd register bank
is made to refer to _firq_stack.
This allows for the FIRQ handler to use its own stack.
Fast Interrupts cannot be used after sleep if this information
is not restored.

This patch adds the suspend and resume functions.

Jira: ZEP-1223

Change-Id: Ic81980f05aee6c1f7b8c46c743f2648c65b29486
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
2016-12-15 12:49:31 +00:00
Julien Delayen
2008af30e7 arc: Define _arc_v2_irq_unit device
Move interrupt initialization for the ARC to its own
device. The init function for the arc will be only
doing platform specific operations

Jira: ZEP-1288

Change-Id: Icb04c3622890021c65cd24cecf6cafee6c37caf9
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
2016-12-15 12:49:30 +00:00
Julien Delayen
60f5d4ef05 arc: Add cc to clobber list for sleep instruction
As flags are modified when entering sleep, add cc to
clobber list.

Jira: ZEP-1408

Change-Id: Ia80bc1c7ddedb9d9963c47108372a90928597c1d
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
2016-12-12 22:06:29 +00:00
Flavio Santes
59c8f32f0f x86/soc: Add ARG_UNUSED macro to avoid compiler warnings
The ARG_UNUSED macro is added to avoid compiler warnings.

Change-Id: If0242548849ee5b258bb3fce9fd727b377411343
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
2016-12-12 20:02:30 +00:00
Marcus Shawcroft
362fb9e62b arm: Fix irq offload inline asm memory ordering.
Add a "memory" clobber to inline asm SVC call to ensure the compiler
does not reorder the instruction relative to other memory accesses.

Issue found by inspect the source code.  There is no evidence to
suggest that this bug will manifest for any current ARM target using a
current compiler.

Change-Id: I32b1e5ede02a6dbea02bb8f98729fff1cca1ef2a
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-12-11 11:19:02 +00:00
Marcus Shawcroft
a94437c03c sensor: Add nRF5 temperature driver.
Basic interrupt driven driver for the nRF5 onboard temperature sensor.

Change-Id: Id0ac303293b8e8b8285b19bcda31284ee6617105
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-12-11 11:14:05 +00:00
Maureen Helm
4a1c31a790 k64: Change the default pinmux driver to the ksdk one
Stop using the specific k64 pinmux driver by default and start using the
more generic ksdk pinmux driver instead.

Jira: ZEP-1393
Change-Id: Id65b59518c386e6ba33cfa5c4c5bd541664d2b41
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2016-12-10 21:14:12 +00:00
Erwan Gouriou
2695efa90a soc: stm32xx: add pwm pinmux support
Following pinmux update for PWM support,
update soc to support this new configuration.

Change-Id: I1126e347ab1ab6b2d830993e548de8f32fa2f8f9
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-12-06 10:31:46 -06:00
Vincenzo Frascino
c4e5126519 soc_beetle: Add initial PM configuration
This patch adds the boot time Power Management configuration for Beetle
on Zephyr. In particular it defines the states of the peripherals during
sleep and deep sleep and the allowed wakeup sources.

Jira: ZEP-1300
Change-Id: Iad9c0f851771ea60d94bbe5420b7b3ee0743b77e
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2016-12-06 10:31:45 -06:00
Neil Armstrong
c14867069a stm32l4: add pinconf settings for I2C
Add one pin configuration for I2C1 of the STM32L4 series.

Change-Id: Id05d916f2a1126ca439aebcddd8dc9c91015f6fe
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-12-06 10:31:45 -06:00
Neil Armstrong
d4b69847a8 stm32l4: add pinconf for USARTs
Add the pin configuration of the USARTs.

Change-Id: Idf7a18b6eab95c61870ad4850c9eafb1fdcab03d
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-12-06 10:31:45 -06:00
Neil Armstrong
3842c60ce3 stm32l4: add clock control driver
Add the clock driver for the STM32L4 series.

Change-Id: Icdf79061f163d8d00187b382d1564422fb875c5b
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-12-06 10:31:41 -06:00
Neil Armstrong
8833e44f6d stm32l4: add initial soc support for stm32l4
Add the initial SoC support for the STM32L4XX family. The code was
tested on STM32L476RG, but should work on any STM32L4XX currently
available.

This implementation was inspired by the stm32f1x implementation.

Change-Id: Id6670bce0c423617284e8467a9c461531f948e0f
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-12-06 09:50:11 -06:00
Erwan Gouriou
2fcf3435c1 serial: Provide new numbering scheme for stm32 UART
There was a misalignment between Zephyr UART device numbering and
SoC UART IP. Device "UART_1" was mapped to IP USART_2, which could
be confusing for user.
This commit allows to align "UART_1" to IP USART_1.
Change is propagated to all STM32F103RB/STM32F401RE based boards and
respective pinmux drivers

Change-Id: Ia8099dfeec7b9c0c686c2a58ccb4dbb1a55b6537
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-12-06 09:50:11 -06:00
Erwan Gouriou
575207c6ff stm32f4: Update after serial driver rework
Due to new serial driver implementation based on STM32Cube we can
remove the USARTX_ADDR defines as they aren't ended anymore

Change-Id: Ia9f9b0a2a63280c0221c789a53ff7338bda17dfb
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-12-06 09:50:11 -06:00
Erwan Gouriou
293b3e18bd stm32f1: Update after serial driver rework
Due to new serial driver implementation based on STM32Cube we can
remove the USARTX_ADDR defines as they aren't ended anymore

Change-Id: Icd5b7995429025c5b54b1a04ca6abb9649ab31c8
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-12-06 09:50:11 -06:00
Erwan Gouriou
8c079e91c9 serial: Provide STM32Cube based serial driver on stm32f1, stm32f4
STM32Cube based implementation allows single driver file for
all stm32 based SoCs.
By maximizing code reuse, use of STM32Cube eases new SoCs
porting into Zephyr and provides better maintanability and
maturity.

Change-Id: Ief4b723add3dfc8b2a839683559c5a4c5d5eb837
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-12-06 09:50:11 -06:00
Flavio Santes
91aa33ba11 arch/x86: Remove unused parameter warning
This patch fixes the unused parameter warning found at the
quark_x1000/soc.h file.

Change-Id: I110d7185d8302f95d14efd13060055e7378aea23
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
2016-12-03 14:49:10 +00:00
Flavio Santes
cf09370d4e arm: Remove unused parameter warning
This patch fixes the unused parameter warning found at the
arch/arm/core/fault.c and arch/arm/soc/st_stm32/stm32f1/soc_gpio.c
files.

Change-Id: I5b3013c1514cff30f4e98feb31169fb28546c534
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
2016-12-03 14:49:09 +00:00
Ramesh Thomas
3cabbfd081 quark_se_ss: power_mgmt: fix sleep mem ordering bug
Memory access could be reorderd around sleep. Add memory
in clobber list.

Jira: ZEP-1408
Change-Id: I49df2542e0059ba76a262fbda58eb46b86e89bea
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-12-03 13:50:31 +00:00
Chuck Jordan
cd198764ba arc: branch too far when STACK_CHECKING enabled.
A build error was resulting if CONFIG_ARC_STACK_CHECKING is enabled.
There is a breq that was too far. Adding conditional code to
re-arrange the branching so that it can be done.

See ZEP-1116.

Change-Id: Idea85817b2e05617bbaa4450437aa74c5737e213
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-12-02 22:57:14 +00:00
Ramesh Thomas
aae7ac0765 quark_se_ss: power_mgmt: Remove redundant int trigger setting
Zephyr is always setting irqs to be level triggered as
required by the core. It is unnecessary to set it to
level again while entering sleep states.

Change-Id: I10f919d619af2e1ab05dc85a67766929b6ae9402
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-12-02 14:03:06 +00:00
Benjamin Walsh
4e8a54c1e3 arc: move disabling/invalidation of caches earlier
Too much code might run with a stale icache, before _PrepC(), so move
the invalidation/disabling code earlier. The asm code does the exact
same thing disable_icache() and invalidate_dcache() were doing.

Change-Id: If52f4e4a1de546fb82873c91ead95614a44b106d
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-30 23:47:46 +00:00
Marcus Shawcroft
64c69d585f Fix Kconfig formatting.
Change-Id: I5720efb9455740a95ea785b0cd205875a215b922
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-11-30 17:01:46 +00:00
Andrew Boie
452fd7a5c2 x86: don't set segment registers if we don't set GDT
We have no idea what's in the GDT if we don't set it ourself.

Change-Id: I3c2e406370e3ea149252c423d66c97aab95bee17
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-29 14:51:57 -08:00
Benjamin Walsh
eba017632a arm/frdm_k64f: fix boot issue with MBED bootloader and INIT_STACKS=y
Initializing the interrupt stack before initializing (turning off) the
watchdog on the FRDM board pushed the initialization of the watchdog too
late, causing it to fire and reset the board. The board would be kept in
a reboot loop.

Move the initialization of the watchdog earlier: this runs on the main
stack now, instead of the interrupt stack, the same stack the interrupt
stack initalization code runs on.

Change-Id: Ic0006f4f4f4090393571d8355a80dc9390c9fbc6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-28 18:33:11 +00:00
Ramesh Thomas
87a2b02189 quark_se_ss: power_mgmt: Fix a bug in call to sleep instruction
When sleep instruction is called with interrupts enabled, the
interrupt priority threshold bits need to be set. Only interrupts
with equal or higher priority will wake the sleep. Currently it
is set to 0 unintentionally and only priority 0 interrupt can
wake the sleep.

Jira: ZEP-1349
Change-Id: I927e259345cc37c5ecc4dfdcde996dd16443e61b
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-11-28 01:00:35 +00:00
Ramesh Thomas
4a09593714 quark_se: power_mgmt: Fixes a cpu context save bug
The cpu context save function was manipulating stack and
returning to C caller. This can corrupt stack if the calling
function has data saved and it pops before entering deep
sleep. Moved sleep functions into assembly to avoid this.

Jira: ZEP-1345
Change-Id: I8a6d279ec14e42424f764d9ce8cbbef32149fe84
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-11-28 00:59:51 +00:00
Vinayak Chettimada
a100ada866 drivers: timer: nRF SoC Series RTC system clock implementation
The nRF5x series SoCs do not implement systick, hence we disable
CORTEX_M_SYSTICK.
Instead, use nRF SoC Series NRF_RTC1 for system clock interfaces.
The kernel system clock interface is implemented using the low
power real time counter NRF_RTC1. NRF_RTC0 is used by the BLE
controller.

In addition, cleanup nRF5x series defconfig to be consistent.

Jira: ZEP-742
Jira: ZEP-1308
Jira: ZEP-1315

Change-id: I0f6cc1836fe0820a65f2cbb02cf5ae7e9eb92e1d
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-11-27 19:39:27 +00:00
Anas Nashif
92c5f91413 arm: systick: Some SoCs do not have systick
Make the systick feature optional that can be selected by the SoC.

Change-Id: I4a405640b84daecc17fc1882743d3cafb78ff861
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-11-27 19:39:26 +00:00
Benjamin Walsh
8641c9e6a5 arm: fix bug when Zero Latency Interrupts are enabled
An IRQ would always register as a ZIL interrupt.

Change-Id: If82a85f472a60512745652aacc7e8b7dfacaa268
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-26 14:04:19 +00:00
Benjamin Walsh
6741561ae4 arc: fix missing _firq_stack symbol when INIT_STACKS=y and NUM_BANKS=1
There is no FIRQ stack in the system in this case, so do not initialize
it.

Change-Id: I8bc068ce43ac8a39909994d8cc01ba0c6a17f4ae
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-26 14:04:19 +00:00
Benjamin Walsh
b2974a666d kernel/arch: move common thread.flags definitions to common file
Also remove NO_METRIC, which is not referenced anywhere anymore.

Change-Id: Ieaedf075af070a13aa3d975fee9b6b332203bfec
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-26 14:04:18 +00:00
Benjamin Walsh
194f45cc66 arm: fix early boot on Cortex-M0 with init stack
The assembler was passed immediate values that are too large for the
limited Cortex-M0 thumb assembly. Load values in registers instead of
using immediate values.

Change-Id: Ib5541c92dea03e0efb1b88ab91eeb408d151a71b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-24 01:45:00 +00:00
Vincenzo Frascino
9f04723439 arm: Enable REBOOT when RUNTIME_NMI is selected
This patch enables REBOOT when RUNTIME_NMI is selected via defconfig
file. This action is required to prevent compilation errors.

Change-Id: I67c18b2860ac34ba8f96e780737b4857a6063ece
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-11-23 20:13:51 -05:00
Vinayak Chettimada
3bc143962c arm: make _timer_int_handler optional
If CORTEX_M_SYSTICK is not selected, do not reference
_timer_int_handler. SoC will need to define a custom system
clock implementation.

Change-Id: I655f3abf66953e434fef69ed16db2d9c2dcc486e
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-11-23 20:13:31 -05:00
Vincenzo Frascino
4d8c021820 arm: Fix CONFIG_RUNTIME_NMI behavior
Zephyr kernel is unable to compile when CONFIG_RUNTIME_NMI is enabled in
defconfig on ARM's architectures.

This patch addresses the following issues:
* In nmi.c _DefaultHandler() is referencing a function
(_ScbSystemReset()) not defined in Zephyr. This has now been replaced
with sys_arch_reboot.
* nmi.h is included in ASM files and due to the usage of "extern" the
compilation ends with an error. Added the directive _ASMLANGUAGE to
prevent the problem.

Jira: ZEP-1319
Change-Id: I7623ca97523cde04e4c6db40dc332d93ca801928
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2016-11-23 00:27:56 +00:00
Benjamin Walsh
069fd3624e kernel: streamline initialization of _thread_base and timeouts
Move _thread_base initialization to _init_thread_base(), remove mention
of "nano" in timeouts init and move timeout init to _init_thread_base().
Initialize all base fields via the _init_thread_base in semaphore groups
code.

Change-Id: I05b70b06261f4776bda6d67f358190428d4a954a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-23 00:27:42 +00:00
Benjamin Walsh
50eb51a745 arc: support interrupt/FIRQ stacks with CONFIG_INIT_STACKS
Use the main stack during very early boot so that we can call memset on
the interrupt and FIRQ stacks. Iniitalize the them before one of them is
used for the rest of the pre-kernel initialization.

Change-Id: Ib57856a66273dda9382e08fa91da5a54847b77c2
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-23 00:24:01 +00:00
Benjamin Walsh
0c9268784e arm: support interrupt stack with CONFIG_INIT_STACKS
Use the main stack during very early boot so that we can call memset on
the interrupt stack. Initialize the interrupt stack before it is used
for the rest of the pre-kernel initialization.

Change-Id: I6fcc9a08678afdb82e83465cda1c7a2a8c849c9b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-23 00:24:01 +00:00