Commit graph

5846 commits

Author SHA1 Message Date
Erwan Gouriou
8986f33559 soc: stm32f407xg: rename SOC config flag
Rename SOC_STM32F407XX to SOC_STM32F407XG to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file).

Change-Id: I0afa16e86b7c99b9e685004f96beeb888f9e7568
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-05-15 13:22:54 -04:00
Erwan Gouriou
2a10920aaf soc: stm32f429zi: rename SOC config flag
Rename SOC_STM32F429XX to SOC_STM32F429XI to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file)

Change-Id: Id188b7703d2bce0a3ded09132ff0f205efa9c143
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-05-15 13:22:54 -04:00
Erwan Gouriou
19a91c0272 soc: stm32l476rg: rename SOC config flag
Rename SOC_STM32L476XX to SOC_STM32L476XG to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file)

Change-Id: I834bb5b83c24c39e90c0492a2b22a7c7802de361
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-05-15 13:22:54 -04:00
Neil Armstrong
558d50242d arm: stm32l432: Switch to STM32L432XC to retain flash size
The xC tag in the SoC reference indicates the flash size, use it in the
configuration to permit selection of correct flash size for dts.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-05-15 13:22:54 -04:00
Vincenzo Frascino
051da9fd4a dts: mps2_an385: Add ARM CMSDK support
This patch adds device tree support for ARM CMSDK IPs on MPS2
AN385.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-15 10:51:13 -05:00
Vincenzo Frascino
df3cec7641 dts: v2m_beetle: Add GPIO support
This patch adds the ARM CMSDK GPIO support to the V2M Beetle
device tree.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-15 10:51:13 -05:00
Vincenzo Frascino
f906e7b099 dts: v2m_beetle: Add DualTimer support
This patch adds the ARM CMSDK DualTimer support to the V2M Beetle
device tree.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-15 10:51:13 -05:00
Vincenzo Frascino
2fe95044c2 dts: v2m_beetle: Add Timer support
This patch adds the ARM CMSDK Timer support to the V2M Beetle device
tree.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-15 10:51:13 -05:00
Vincenzo Frascino
8219923c26 dts: v2m_beetle: Add WDOG support
This patch adds the ARM CMSDK WDOG support to the V2M Beetle device
tree.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-15 10:51:13 -05:00
Vincenzo Frascino
603c826fa4 dts: v2m_beetle: Generate Uart base addr
This patch enables the generation of the ARM CMSDK UART base address
from the device tree.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-15 10:51:13 -05:00
Andrew Boie
5dcb279df8 debug: add stack sentinel feature
This places a sentinel value at the lowest 4 bytes of a stack
memory region and checks it at various intervals, including when
servicing interrupts or context switching.

This is implemented on all arches except ARC, which supports stack
bounds checking directly in hardware.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-13 15:14:41 -04:00
Andrew Boie
9175d20ceb arc: fix CONFIG_ARC_STACK_CHECKING
- There's no clear need to disable frame pointers if this feature is
used, remove this directive.
- The 'top' and 'base' terms are reversed. The 'base' is the high
address of the stack. The top is the lowest address, where we cannot
push further down. Fixup member and offset names to correspond to how
these terms are used in hardware documentation.
- Use correct pointers for stack top location
- Fatal exceptions now go through _NanoFatalErrorHandler to report the
faulting ip and thread.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-13 15:14:41 -04:00
Andrew Boie
174f301147 build: simplfy how extra build steps are specified
For various reasons its often necessary to generate certain
complex data structures at build-time by separate tools outside
of the C compiler. Data is populated to these tools by way of
special binary sections not intended to be included in the final
binary. We currently do this to generate interrupt tables, forthcoming
work will also use this to generate MMU page tables.

The way we have been doing this is to generatea "kernel_prebuilt.elf",
extract the metadata sections with objcopy, run the tool, and then
re-link the kernel with the extra data *and* use objcopy to pull
out the unwanted sections.

This doesn't scale well if multiple post-build steps are needed.
Now this is much simpler; in any Makefile, a special
GENERATED_KERNEL_OBJECT_FILES variable may be appended to containing
the filenames to the generated object files, which will be generated
by Make in the usual fashion.

Instead of using objcopy to pull out, we now create a linker-pass2.cmd
which additionally defines LINKER_PASS2. The source linker script
can #ifdef around this to use the special /DISCARD/ section target
to not include metadata sections in the final binary.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-13 14:07:09 -04:00
Andrew Boie
3d3d6a85df x86: remove hacks to include functions
None of this is currently necessary, the spurious interrupt
stubs and exception entry code is included in the binary just
fine. To make matters worse, some data referenced lives in the
.intList section which is completely stripped out of the binary.

If in the future we find certain essential functions are being
garbage collected when they should not be, the proper way to
mitigate this is with KEEP() directives in the linker script.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-13 14:07:09 -04:00
Andrew Boie
51df312abc xtensa: merge crt1-*.S
We had two assembly files to prepare for entry into C domain,
one intended for the simulator and one intended for real boards.

- Both files merged into a single crt1.S for either simulated or real
  targets
- Extra logic to populate command line arguments from simulator removed,
  we don't use it.
- BSS zeroing logic from crt1-boards.S used
- Reference to missing reset-unneeded.S removed
- exit() implementation moved to fatal.c, now invokes a kernel panic
  if we are not running under the simulator

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-12 12:56:12 -04:00
Andrew Boie
b7aa6b7bd0 xtensa: optionally build reset vector code
In real-world use-cases this isn't always needed.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-12 12:56:12 -04:00
Anas Nashif
f628c12b04 xtensa: rename SOC_SAMPLE_CONTROLLER
SOC_SAMPLE_CONTROLLER option name is too generic, make it Xtensa
specific to avoid confusion.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-05-12 07:00:04 -04:00
Andrew Boie
d26cf2dc33 kernel: add k_thread_create() API
Unline k_thread_spawn(), the struct k_thread can live anywhere and not
in the thread's stack region. This will be useful for memory protection
scenarios where private kernel structures for a thread are not
accessible by that thread, or we want to allow the thread to use all the
stack space we gave it.

This requires a change to the internal _new_thread() API as we need to
provide a separate pointer for the k_thread.

By default, we still create internal threads with the k_thread in stack
memory. Forthcoming patches will change this, but we first need to make
it easier to define k_thread memory of variable size depending on
whether we need to store coprocessor state or not.

Change-Id: I533bbcf317833ba67a771b356b6bbc6596bf60f5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-11 20:24:22 -04:00
Anas Nashif
09b239102a xtensa: xt-sim: mark it as a board with simulator features
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-05-11 16:51:56 -04:00
Max Filippov
4b8419e420 xtensa: drop references to C library
C library is not actually used by the xtensa port, we only need the
'exit' function. Implement 'exit' in crt1-* and drop remaining
references to the C library.

Change-Id: I8a562363956b4755a6b5baee7acf3726485e5ce3
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-05-11 16:51:56 -04:00
Max Filippov
0538dc1a1c xtensa: make sample_controller runnable on QEMU
Add QEMU_CPU_TYPE for the sample_controller, so that zephyr image could
be run on QEMU with sample_controller core.

Change-Id: Id9e97a43c4b7921142289dcf97ff782993ca0463
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-05-11 16:51:56 -04:00
Max Filippov
6a89999787 xtensa: use inline assembly instead of XT_* macros
XT_* macros are defined in xtensa HAL headers as xcc intrinsics. gcc
does not have any of these intrinsics. Replace XT_* macros with inline
assembly or provide gcc-compatible definitions.

Change-Id: If823ea8a7898a11a3a8363b17efdba27dee4c6a4
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-05-11 16:51:56 -04:00
Andrew Boie
f57e79b6d5 xtensa: remove Kconfig.cores
This file is no longer used by the build system.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-11 12:47:23 -04:00
Andrew Boie
99c89e17e3 xtensa: fix coprocessor save area
A bad rebase of a patch that moved these defines around
unintentionally reverted a necessary change to the coprocessor
save area.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-11 12:47:23 -04:00
Vincenzo Frascino
255f19891a dts: mps2_an385: Initial device tree support
This patch adds the intial device tree support to V2M MPS2 AN385
platform.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-09 11:16:52 -04:00
Neil Armstrong
092be24061 arm: stm32l4: Add configuration and dts for STM32L432XX
Add configuration and dts for the STM32L432XX SoC STM32L4 variant.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-05-08 15:03:15 -04:00
fallrisk
20f41814de arch: Add Atmel SAM4S SoC support
Added support for Atmel SAM4S (Cortex-M4) MCU:
- Kconfig files
- Devicetree files

Signed-off-by: Justin Watson <jwatson5@gmail.com>
2017-05-08 15:03:15 -04:00
fallrisk
44c421b4a3 boards: arduino_due: Added DTS to the Arduino Due.
Change-Id: I006f9d4080a1351534ede5cc601e43526c39aa83
Origin: Original
Signed-off-by: Justin Watson <jwatson5@gmail.com>
2017-05-08 15:03:15 -04:00
Piotr Mienkowski
38d8c863d4 arm: dts: Add DTS support for SAME70 SoC
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-05-05 16:44:41 -05:00
kontais
3b0b7671a0 stm32f4/arm_mpu_mem_cfg.h compile error fix
Signed-off-by: kontais <kontais@aliyun.com>
2017-05-05 10:13:08 -05:00
Justin Watson
558281b096 arch: sam3x: update Kconfig options after move to SAM SoC family tree
The files for the Arduino Due needed to be updated to use the new
configuration when the SoC moved from the atmel_sam3 directory to
the atmel_sam/sam3x directory.

Jira: ZEP-2067

Signed-off-by: Justin Watson <jwatson5@gmail.com>
2017-05-03 13:51:37 -04:00
Jon Medhurst
14ce362972 boards: mps2_an385: Enable I2C devices
The FPGA on the MPS2 board implements 4 SBCon devices for I2C which are
connected to:
- a touchscreen controller
- the audio device (for configuration)
- both shield connectors

Change-Id: I55ca985e18b45d68f5e7421c4768dfc9bf2fcb3f
Signed-off-by: Jon Medhurst <tixy@linaro.org>
2017-05-03 13:51:37 -04:00
Adithya Baglody
d03b2496cd test: benchmarking: Timing metrics for the kernel
JIRA: ZEP-1822, ZEP-1823, ZEP-1825

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-05-03 08:46:30 -04:00
Kumar Gala
ac0bb050dd arm: dts: ti_lm3s6965: Add device tree support for Stellaris UART
Converted Stellaris UART driver over to utilize device tree generated
defines.  Added a yaml description for the uart, and converted over the
ti_lm3s6965 SoC & qemu_cortex_m3 board port over to utilize it.

Change-Id: Ie20844eb63d2c68eb59ad4160f7f5b5a35e2943b
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:40 -05:00
Kumar Gala
f6284cfbec arm: dts: ti_lm3s6965: Add Device Tree Support
Introduce a simple device tree for the TI lm3s6965 SoC and QEMU
Cortex-M3 board port.  We get flash and memory base addresses and sizes
from the device tree as well as the ARM NVIC number of priority bits.

Change-Id: I4452b5543de7be55518997e54837ccbfd4f121df
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:40 -05:00
Florian Vaussard
45dde7eb3f arm: stm32f4: Reorder Kconfig options
Reorder config entries alphabetically to make it easier to add new ones.

Change-Id: Ib118405a150a408638232513fba7198b458ecfa7
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
2017-04-28 15:26:39 -05:00
Kumar Gala
a22e5924b5 arm: dts: nrf: Remove !HAS_DTS Kconfig bits
Now that all the nRF based board/SoCs have device trees, we can remove
the Kconfig bits that are now coming from device tree.

Change-Id: Ia1a870a50582d4109070d2833660f58fd6f8691f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:39 -05:00
Kumar Gala
ca3c7ec0a9 arm: dts: nrf: Add Device Tree Support for nRF51822 SoC & boards
Add device tree support for nRF51822 SoCs and Arduino 101-BLE,
Curie-BLE, BLE Nano, PCA10028-DK, and Quark-SE BLE boards. This
is minimal support for memory, flash, and UART.

Change-Id: I7e572bea537e384b6d66e520462f023ace0c9b35
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:39 -05:00
Kumar Gala
9b30a9b308 arm: dts: nrf: Fixup nRF52840-QIAA SoC support for device tree
Fixup the nRF52840-QIAA to allow getting its SRAM & FLASH sizes from
device tree.

Change-Id: I67ecd7da5f0472402064f158030d9f97f49d7d20
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:39 -05:00
Kumar Gala
62b0750499 arm: soc: ti_lm3s6965: remove dead code
Nothing calls _ScpMainOscEnable, so lets remove it and associated files
that aren't used anymore.

Change-Id: Ibe900d039c531c4da56baa673d309ee961b09e52
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:38 -05:00
Kumar Gala
62d2d362ac arm: nxp: kl2x: Move to using UART_MCUX_LPSCI for UART0
Cleanup soc code to enable UART_MCUX_LPSCI to support UART0.

Change-Id: I173febffcffc902f228946124e0434f122a67607
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:38 -05:00
Kumar Gala
ed467a695a serial: mcux: Shim driver for LPSCI UART on KL25Z
Adds a shim layer around the mcux lpsci driver to adapt it to the Zephyr
serial interface.

Change-Id: I024f1605e3194f34bb57e8a121900e05b3085a82
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:38 -05:00
Erwan Gouriou
eee56a7c10 soc: stm32l4xx: add support for STM32L475XG
Add support for STM32L475xG SoC as a preliminary for
Discovery IOT board support.
stm32l476.dtsi file is now including stm32l475.dtsi
since STM32L476 SoC is a STM32L475 SoC with LCD support

Change-Id: I7567255e4172231cbf4899474617ecae0cd68d64
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-04-28 15:26:38 -05:00
Erwan Gouriou
242ed389a3 stm32f4: Clean references to stm32f4 specific clock control
Following activation of stm32 common clock driver for stm32f4 series
remove references to stm32f4 specific driver.

Change-Id: I372a0ea046007bcb34944d6b2b8880077583b1d3
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-04-28 15:26:11 -05:00
Erwan Gouriou
80b7bec12c soc: stm32f4: Enable LL based clock control
This commit disables native stm32f4x clock control
driver and enables stm32 LL clock control driver
for stm32f4 family

Jira: ZEP-2039

Change-Id: I98ba6c89c4a3a1f39658c5808cd47a2d1f344130
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-04-28 15:26:11 -05:00
Erwan Gouriou
fda01e52c2 drivers: clock control: Provide LL based clock control for stm32f4 series
This commit enables STM32Cube LL based driver for stm32f4 series.
This generic driver provides a unified API to clock driver for all
stm32 series.
LL API allows driver to be lightweight and to keep genericity across
stm32 family to ease further devlopment and maintenance.

Change-Id: Ie31ae8f433313787f9c9eda77de41925721d54dd
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-04-28 15:06:41 -05:00
Gil Pitney
c73a1eb806 cc3220sf: Add support for the TI CC3220SF SoC
The CC3220SF is a replacement for the CC3200 SoC, comprising
a network coprocessor and Cortex-M4 MPU.

This leverages the CC3220 SDK driver peripheral library in ROM,
and some files built from ext/hal/ti/.

Jira: ZEP-1958

Change-Id: I892b212c178e05d84ff1d716dde593ced653ae6d
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2017-04-28 15:06:41 -05:00
Mazen NEIFER
51eb081311 xtensa port: Fixed crash on interrupt handlers when logger is enabled.
This fixes ZEP-1955. The issue was that the interrupt stack frame only
allocates 4 registers. This means that if any window overflow happens,
only 4 registers can be saved. This implies that the interrupt handler
can not call functions other than using call4. If this rule is not
honored, then it will result in the registers being overwriting other
context information and thus a stack corruption.

The fix consists on using call4 for calling even t logger function,
which is by the way more optimal as the interrupt handler does not need
to save more than 4 registers when these functions are called.

Issue: ZEP-1955

Change-Id: Iacea626443d1d61d95a52253ac8ff15fc3722d2c
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-28 15:49:01 +00:00
Andrew Boie
8bfee13cd3 x86: define MMU data structures
This was more or less transplanted from old Viper codebase (Zephyr's
ancestor which supported paging) and adapted to current coding style.

Change-Id: I203e631f1dcd5f2fb4e9a2fa9339fc7521c7962d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-27 17:46:54 +00:00
Ramesh Thomas
89ffd44dfb kernel: tickless: Add tickless kernel support
Adds event based scheduling logic to the kernel. Updates
management of timeouts, timers, idling etc. based on
time tracked at events rather than periodic ticks. Provides
interfaces for timers to announce and get next timer expiry
based on kernel scheduling decisions involving time slicing
of threads, timeouts and idling. Uses wall time units instead
of ticks in all scheduling activities.

The implementation involves changes in the following areas

1. Management of time in wall units like ms/us instead of ticks
The existing implementation already had an option to configure
number of ticks in a second. The new implementation builds on
top of that feature and provides option to set the size of the
scheduling granurality to mili seconds or micro seconds. This
allows most of the current implementation to be reused. Due to
this re-use and co-existence with tick based kernel, the names
of variables may contain the word "tick". However, in the
tickless kernel implementation, it represents the currently
configured time unit, which would be be mili seconds or
micro seconds. The APIs that take time as a parameter are not
impacted and they continue to pass time in mili seconds.

2. Timers would not be programmed in periodic mode
generating ticks. Instead they would be programmed in one
shot mode to generate events at the time the kernel scheduler
needs to gain control for its scheduling activities like
timers, timeouts, time slicing, idling etc.

3. The scheduler provides interfaces that the timer drivers
use to announce elapsed time and get the next time the scheduler
needs a timer event. It is possible that the scheduler may not
need another timer event, in which case the system would wait
for a non-timer event to wake it up if it is idling.

4. New APIs are defined to be implemented by timer drivers. Also
they need to handler timer events differently. These changes
have been done in the HPET timer driver. In future other timers
that support tickles kernel should implement these APIs as well.
These APIs are to re-program the timer, update and announce
elapsed time.

5. Philosopher and timer_api applications have been enabled to
test tickless kernel. Separate configuration files are created
which define the necessary CONFIG flags. Run these apps using
following command
make pristine && make BOARD=qemu_x86 CONF_FILE=prj_tickless.conf qemu

Jira: ZEP-339 ZEP-1946 ZEP-948
Change-Id: I7d950c31bf1ff929a9066fad42c2f0559a2e5983
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2017-04-27 13:46:28 +00:00