This commit introduces the support for the standard Zicntr extension, which
provides hardware counters.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds the support for the following new Zc* series compressed
instruction extensions:
Zca - Subset of the C extension without FP loads and stores
Zcb - "Simple" instructions
Zcd - Double-precision floating-point instructions
Zcf - Single-precision floating-point instructions
Zcmp - "Complex" instructions for embedded CPUs
Zcmt - Table jump instructions for embedded CPUs
With the introduction of the Zc* extensions, the C extension now implies
the following Zc* extensions:
* Zca, always
* Zcf if F is specified (RV32 only)
* Zcd if D is specified
The Zc* extensions that are implied by the C extension are not specified in
the GCC `-march` flag because they are redundant and can interfere with the
resolution of the correct multi-lib for the selected architecture unless
the the alternate mappings for the redundant forms are manually specified.
All the implementation details in this commit are based on the Zc* v1.0.0
specification, which is the ratified version.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Add support for CONFIG_ROM_START_OFFSET on ARC processors. Note that the
arc ISA requires vector table offset to be at a 1024 KiB boundary, so
the default ROM_START_OFFSET when using MCUBoot must be increased.
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
Add CONFIG_ARCH_SUPPORTS_ROM_OFFSET, a convenience Kconfig to indicate
that CONFIG_ROM_START_OFFSET is supported on this architecture
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
z_arm_save_fp_context and z_arm_restore_fp_context
save and restore fpu context regardless of the
CONFIG_FPU_SHARING setting.
This modification is required to support suspend to ram use cases
where save and restore of FPU state is needed to ensure proper bahaviour
after wakeup.
Signed-off-by: Michele Sardo <michele.sardo@st.com>
Added configurable support for L1 cache region operations,
which offers improved performance over line operations.
Added configurable support for SLC (system level cache).
Added support for entire cache operations: flush_all,
invd_all, flush_and_invd_all.
Reviewed-by: Aaron Komisar <aaron.komisar@tandemg.com>
Signed-off-by: Yanir Levin <ylevin@gsitechnology.com>
CONFIG_NATIVE_APPLICATION, which represents the way in which
native_posix and its kin were built, was deprecated in 4.1 after the
introduction of native_sim and CONFIG_NATIVE_LIBRARY.
We remove support for it now for 4.3.
Let's remove the architecture layer adaptation code and cmake support.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add missing call to thread_switched_in for the purpose of tracing.
Fixeszephyrproject-rtos/zephyr#76057
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
When LTO is enabled, linker may relocate literal pools out of Thumb LDR
instruction's reach causing "offset out of range" errors while linking.
This commit adds `.ltorg` directive in the inline asm blocks where absolute
addresses are loaded using the `ldr` instructions, in order to ensure that
the literal pool containing the absolute addresses are placed near the
`ldr` instructions.
Note that the `.ltorg` directive is recognised by all toolchains supported
by Zephyr and no toolchain abstraction is provided for now.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Utilize a code spell-checking tool to scan for and correct spelling errors
in `Kconfig` files within the `arch`, `boards`, `kernel`, `modules`,
`samples`, and `share` directory.
Additionally, incorporates a fix recommended by the reviewer.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Floating-Point System ID register (FPSID) = 0x41033094
AArch32 Media and VFP Feature Register 0 (MVFR0) = 0x10110222
AArch32 Media and VFP Feature Register 0 (MVFR1) = 0x1111111
MVFR1 SIMDFMAC, bits [31:28] = 0; FMAC is not supported
Signed-off-by: Simon Maurer <mail@maurer.systems>
The RX linker is using the name "data" for .data region start
which caused the application cannot use "data" for variable
naming globally.
This commit change the name to "__data_region_start" as expected
in the linker_defs.h file
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Update a comment about GDB use of register index and "regno"
parameters. Only some GDB versions use "idx" instead of "regno."
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
To report unavailable registers to the GDB client, the GDB stub has
to return a string like "xx" in the value string.
Signed-off-by: Noah Klayman <noah.klayman@intel.com>
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Move an assignment performed on both "if" branches as the last
operation to after the "if."
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
As per Zephyr guidelines regarding the use of inclusive language, apply
the following replacements:
- s/master/primary/g
- s/slave/secondary/g
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This is an X86 specific option and should not appear as generic debug
option.
Fixeszephyrproject-rtos/zephyr#52929
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add semihosting support for Xtensa architecture.
Existing semihosting instructions are based on ARM, so they are
converted to Xtensa codes before the semihosting call is invoked.
Return codes of read, write and seek calls had to be converted to match
semihosting API definitions.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Move semihost_x_args structs to include/semihost_types.h so that
semihost implementations can access their elements if needed.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
When calling device_get_binding(NULL) from userspace, this eventually
funnels down to a call to arch_user_string_nlen() where it tried to
verify that the kernel has access to this address (0x0). But since
this originates from userspace, we really want to know if this is
accessible from userspace, so using arch_buffer_validate() instead
of xtensa_mem_kernel_has_access() is preferable.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Support booting from any usable core in systems with partially
fused-off CPUs. Update get_cpu_logic_id to iterate over the actual
number of enabled CPUs using DT_CHILD_NUM_STATUS_OKAY(DT_PATH(cpus))
instead of CONFIG_MP_MAX_NUM_CPUS.
Resize the voting[] array based on DT_CHILD_NUM_STATUS_OKAY to ensure
each CPU can vote correctly.
Signed-off-by: urvashi sharma <urvashis@qti.qualcomm.com>
This fixes GDB backtracing by forcibly spilling all registers,
and faking values for WINDOWSTART and WINDOWBASE. This is
effectively telling GDB that only A0-A3 and AR0-AR3 contain
active data and other physical registers do not. GDB then must
rely on spilled values on stack. Otherwise, GDB will try to
look at all AR* registers for previous frame(s). Since we
do not save all AR* register values, there is nothing for GDB
to look at, and thus failing to unwind stack.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Inside copy_to_ctx(), we are typecasting the stack pointer into
a 32-bit array pointer, and there was unbalanced const between
two sides. Since we should not be modifying anything inside
that array, add const to the 32-bit array pointer too. So now
the compiler will not complain about discarding the const
qualifier.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The calculation of number of high registers is not entirely
correct. We need to get past the pointer to BSA in the stack
frame before reaching the high registers. The location address
difference between the BSA and start of high registers then
can be used to calculate how many high registers in the stack
frame. So correct the start location of high registers in
the calculation as it was incorrect before. Though the result
would be the same as further divisions would mask this error.
However, it is better to correct this for readability.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
With experience it becomes clear, that failing to resolve symbols
during the linking process is likely fatal for the module loading and
a simple warning isn't enough. Fail loading instead.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
When not using dynamic interrupt mapping, various interrupt tables are
configured to be stored in read-only memory in the linker script.. Mark
them const so that the linker doesn't complain.
This affects _sw_isr_table, _irq_vector_table, and z_shared_sw_isr_table in
arch/common along with _VectorTable in arch/arc.
Signed-off-by: Keith Packard <keithp@keithp.com>
move mov r7, #0 to use it on both branches as aarch64
implementation uses wzr which returns 0 on read
but r7 might have an undefined value after a reset.
Signed-off-by: Julien Racki <julien.racki@st.com>
The difference between __irq_disable() and irq_lock() is that the former
essentially translates to `cpsid i`, whereas `irq_lock()` translates to
setting BASEPRI (on cores with BASEPRI). This means that using
irq_lock() does not disable zero-latency interrupts (ZLIs), which
reduces the potential execution latency of ZLIs.
In both isr_wrapper and _arch_isr_direct_pm() (which is just
really an implementation of ISR_DIRECT_PM()), we were using
__irq_disable() to disable all interrups, including ZLIs. But the code
executed with interrupts disabled handles waking up from idle, and so
must only be protected against regular interrupts being executed, not
ZLIs, which should have no effect on the correct execution of the code.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
