This fix removes the zephyr/ prefix from linker included files.
With this prefix the build works only for Ninja and not for
other build tools.
Linking in Zephyr / CMake:
- Ninja invokes linking directly from <build>.
- Make invokes linking form <build>/zephyr.
The linker default uses cwd for looking up INCLUDE directives if not found
in list of includes.
Zephyr always adds <build>/zephyr as link include using CMake,
and this is passed to ld as -L<build>/zephyr therefore using
INCLUDE isr_tables_swi.ld ensures it will be correctly found in all cases.
Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
This commit removes the need of swi_tables.ld file if the
ISR table generator is not configured to use it.
Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
This commit updates the arm and arm64 architecture files
to support the new ISR handlers creation parser.
Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
This commit implements the possibility to locally create an interrupt
table entry. This changes the way interrput table is created,
now it should not be created as an source file but rather it would be
constructed by the linker.
Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
This commit moves all the functionality related to the current
interrupt parser into gen_isr_tables_parser_carrays.py file.
The new parser file gen_isr_tables_parser_local.py file is
implemented with the new parser that.
Additional information added to the generated interrupt header
that contains data required by the new parser.
Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
This commit updates the definition of z_shared_isr_table_entry
to use _isr_table_entry instead of specially created z_shared_isr_client.
Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
This commit adds missing __used attribute it int_list_header,
preventing it from being optimized out.
Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
The ZSR_FLUSH scratch register is only needed if kconfig
CONFIG_KERNEL_COHERENCE is enabled. So update gen_zsr.py
for that.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Print THREADPTR when dumping stack just like other registers.
There is no need to guard that behind CONFIG_USERSPACE.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
add interface for encode irq flags from acpica to arch specfic.
Currently enabled only for x86 archiecture.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
Disable Thread Local Storage for some configurations of ARC architecture.
For cores with more then one RGF_NUM_BANKS the parameter is disabled
by-default because banks syncronization requires significant time,
and it slows down performance.
Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
In case of ARCv3 we have shared cache disabled after
reset (in ARCv2 it was enabled by default). Let's
enable it at early boot phase (if it's available in HW).
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
ARCv3 processors have HW prefetch feature which is disabled
after reset. Let's enable it.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
When COMPILER_WARNINGS_AS_ERRORS is set, let's also have the
native simulator runner (and anything Zephyr requests built with it)
be built with the same option to treat warnings as errors.
Otherwise we will miss those by default in CI.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The arm64_cpu_boot_params will be read on other cores
call sys_cache_data_flush_range flush the data from the cache to RAM.
This ensures that other cores can access the correct data.
Signed-off-by: honglin leng <a909204013@gmail.com>
Do not define these macros globally, but instead
define them only for this library and when needed.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This constant is supposed to be defined as a long instead of an int,
presumably to support systems where int isn't large enough.
Signed-off-by: Keith Packard <keithp@keithp.com>
Disabling the MPU doesn't clear regions configuration. There is a risk
in multi-image environment that there are some old region setting e.g.
stack guard. This may cause a memory fault, because of different images
layout e.g. RO/RW.
Just clear and disable all regions configuration before the new
initialization.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
It looks like all SoCs in tree check if an exception comes from an IRQ
the same way, so let's provide a common logic by default, still
customizable if the SoC selects RISCV_SOC_ISR_CHECK.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
It looks like some soc_offsets.h files need to be included before
kernel_offsets, otherwise there are some header race conditions due to
the infamous soc.h. This problem is exposed if all soc.h are removed
from RISC-V arch header files (see the upcoming commits). It can be
reproduced by building rv32m1_vega_ri5cy board after applying all the
patches in this series (excluding this one, of course).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
There is no need to sync in every xtlb invalidation. Sync only
after all tlb autofill ways invalidation.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Xtensa's arch level atomic implementation requries S32C1I
support which may not exist as Xtensa cores are highly
configurable. Implying CONFIG_ATOMIC_OPERATIONS_ARCH at
arch level has a side effect that it is enabled
regardless if the other options are enabled. Given how
the header file's #ifdef is structured, only C atomic
ops can override this, which means enabling
CONFIG_ATOMIC_OPERATIONS_BUILTIN has no effect at all.
So let the SoC or board decide which atomic ops are
being used instead.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
According to the clic specification
(https://github.com/riscv/riscv-fast-interrupt), the mnxti register has
be written, in order to clear the pending bit for non-vectored
interrupts. For vectored interrupts, this is automatically done.
From the spec:
"If the pending interrupt is edge-triggered, hardware will automatically
clear the corresponding pending bit when the CSR instruction that
accesses xnxti includes a write."
I added a kconfig `RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING` to allow custom
irq handling. If enabled, `__soc_handle_all_irqs` has to be implemented.
For clic, non-vectored mode, I added a `__soc_handle_all_irqs`, that
handles the pending interrupts according to the pseudo code in the spec.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
The irq priority has to be called for dynamic and direct irqs, too. For
direct isrs, this was missing completely, for direct irqs just for the
clic.
For dynamic irqs, I replaced the current implementation with
`z_riscv_irq_priority_set`. For the plic, this is exaclty the same.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
For some reason, unrelated code change triggered compiler
warning about this function returns even though it is
marked nonreturn. So add CODE_UNREACHABLE to silence
the warning, possibly to catch any errors.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
wsr.UPPERCASE can lead to compiler errors when UPPERCASE matches
a macro defined in the special register header file.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
rsr.UPPERCASE can lead to compiler errors when UPPERCASE matches
a macro defined in the special register header file.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Instead of custom SOC_MCAUSE_EXP_MASK definition. Note that SoCs
selecting RISCV_PRIVILEGED already used such config indirectly (see
changes in soc_common.h).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
As defined in Table 3.6 of "The RISC-V Instruction Set Manual, Volume
II: Privileged Architecture". Delete all spread definitions of the same,
weirdly prefixed with "SOC".
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Initial implementation of `sched_getparam()` and `sched_getscheduler()`
POSIX APIs as a part of PSE53 `_POSIX_PRIORITY_SCHEDULING` option group.
Both functions are actually placeholders and just return `ENOSYS`
since Zephyr does not yet support processes or process scheduling.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Because it was exclusively used by the "common" RISC-V privileged code
to build CPU idle routines that are now handled by arch level code.
Also, all platforms defaulted to "y", making it pointless in practice.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
While going to idle may require SoC specific implementations, provide a
more sensible default implementation.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The constant used to calculate TLB entries for the way six was wrong
and causing an integer overflow. Consequently only the first 512MB where
being unmapped from the TLB.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Use the arch-cache functions instead of the sys-cache-functions
in z_arm_init_arch_hw_at_boot to ensure that the caches are
disabled even when CONFIG_CACHE_MANAGEMENT is disabled.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Use sys_cache_data_enable instead of arch_dcache_enable to enable
the cache. This will ensure that CONFIG_CACHE_MANAGEMENT
is considered correctly.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
The interface to flush fpu is not unique to one architecture, make it a
generic, optional interface that can be implemented (and overriden) by a
platform.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Different architecture are doing this in custom ways and using different
naming conventions, unify this interface and make it part of the arch
implementation for SMP.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
