This commit renames the `cortex_r` directory under the AArch32 to
`cortex_a_r`, in preparation for the AArch32 Cortex-A support.
The rationale for this renaming is that the Cortex-A and Cortex-R share
the same base design and the difference between them, other than the
MPU vs. MMU, is minimal.
Since most of the architecture port code and configurations will be
shared between the Cortex-A and Cortex-R architectures, it is
advantageous to have them together in the same directory.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit updates the `xilinx_zynqmp` SoC initialisation code to use
the CMSIS-Core(R) features.
In addition, it also defines the Core IP revision value for the SoC as
specified in the Zynq UltraScale+ Device Technical Reference Manual.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit relocates the exception vector table address range
configuration routine that was previously implemented as part of
Cortex-R architecture reset function to SoC platform-specific
initialisation routine.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based
platform for Cortex-R based testing. This SoC only supports an
interrupt controller and serial port for limited testing.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
