Stack sentinel doesn't prevent corruption, it just notices when
it happens. Any memory could be in a bad state and it's more
appropriate to take the entire system down rather than just kill
the thread.
Fatal testcase will still work since it installs its own
_SysFatalErrorHandler.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
One of the stack sentinel policies was to check the sentinel
any time a cooperative context switch is done (i.e, _Swap is
called).
This was done by adding a hook to _check_stack_sentinel in
every arch's __swap function.
This way is cleaner as we just have the hook in one inline
function rather than implemented in several different assembly
dialects.
The check upon interrupt is now made unconditionally rather
than checking if we are calling __swap, since the check now
is only called on cooperative _Swap(). The interrupt is always
serviced first.
Issue: ZEP-2244
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This places a sentinel value at the lowest 4 bytes of a stack
memory region and checks it at various intervals, including when
servicing interrupts or context switching.
This is implemented on all arches except ARC, which supports stack
bounds checking directly in hardware.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Unline k_thread_spawn(), the struct k_thread can live anywhere and not
in the thread's stack region. This will be useful for memory protection
scenarios where private kernel structures for a thread are not
accessible by that thread, or we want to allow the thread to use all the
stack space we gave it.
This requires a change to the internal _new_thread() API as we need to
provide a separate pointer for the k_thread.
By default, we still create internal threads with the k_thread in stack
memory. Forthcoming patches will change this, but we first need to make
it easier to define k_thread memory of variable size depending on
whether we need to store coprocessor state or not.
Change-Id: I533bbcf317833ba67a771b356b6bbc6596bf60f5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Future tickless kernel patches would be inserting some
code before call to Swap. To enable this it will create
a mcro named as the current _Swap which would call first
the tickless kernel code and then call the real __swap()
Jira: ZEP-339
Change-Id: Id778bfcee4f88982c958fcf22d7f04deb4bd572f
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Historically, space for struct k_thread was always carved out of the
thread's stack region. However, we want more control on where this data
will reside; in memory protection scenarios the stack may only be used
for actual stack data and nothing else.
On some platforms (particularly ARM), including kernel_arch_data.h from
the toplevel kernel.h exposes intractable circular dependency issues.
We create a new per-arch header "kernel_arch_thread.h" with very limited
scope; it only defines the three data structures necessary to instantiate
the arch-specific bits of a struct k_thread.
Change-Id: I3a55b4ed4270512e58cf671f327bb033ad7f4a4f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Unlike assertions, these APIs are active at all times. The kernel will
treat these errors in the same way as fatal CPU exceptions. Ultimately,
the policy of what to do with these errors is implemented in
_SysFatalErrorHandler.
If the archtecture supports it, a real CPU exception can be triggered
which will provide a complete register dump and PC value when the
problem occurs. This will provide more helpful information than a fake
exception stack frame (_default_esf) passed to the arch-specific exception
handling code.
Issue: ZEP-843
Change-Id: I8f136905c05bb84772e1c5ed53b8e920d24eb6fd
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We do the same thing on all arch's right now for thread_monitor_init so
lets put it in a common place. This also should fix an issue on xtensa
when thread monitor can be enabled (reference to _nanokernel.threads).
Change-Id: If2f26c1578aa1f18565a530de4880ae7bd5a0da2
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We do a bit of the same stuff on all the arch's to setup a new thread.
So lets put that code in a common place so we unify it for everyone and
reduce some duplicated code.
Change-Id: Ic04121bfd6846aece16aa7ffd4382bdcdb6136e3
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
There are a few places that we used an naked unsigned type, lets be
explicit and make it 'unsigned int'.
Change-Id: I33fcbdec4a6a1c0b1a2defb9a5844d282d02d80e
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types. This handles the remaining includes and kernel, plus
touching up various points that we skipped because of include
dependancies. We also convert the PRI printf formatters in the arch
code over to normal formatters.
Jira: ZEP-2051
Change-Id: Iecbb12601a3ee4ea936fd7ddea37788a645b08b0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types. There are few places we dont convert over to the new
types because of compatiability with ext/HALs or for ease of transition
at this point. Fixup a few of the PRI formatters so we build with newlib.
Jira: ZEP-2051
Change-Id: I7d2d3697cad04f20aaa8f6e77228f502cd9c8286
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t. This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.
We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.
We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.
Jira: ZEP-2051
Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This private data structure now no longer introduces a typedef or
uses CamelCase. It's not necessary to specify the size of extern
arrays, so we don't need a block of #ifdefs for every arch.
Change-Id: I71fe61822ecef29820280a43d5ac2822a61f7082
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This avoids asm files from having to explicitly define the _ASMLANGUAGE
symbol themselves.
Change-Id: I71f5a169f75d7443a58a0365a41c55b20dae3029
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
They are not part of the API, so rename from K_<state> to
_THREAD_<state>.
Change-Id: Iaebb7d3083b80b9769bee5616e0f96ed2abc5c56
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
These two fields in the thread structure control the preemptibility of a
thread.
sched_locked is decremented when the scheduler gets locked, which means
that the scheduler is locked for values 0xff to 0x01, since it can be
locked recursively. A thread is coop if its priority is negative, thus
if the prio field value is 0x80 to 0xff when looked at as an unsigned
value.
By putting them end-to-end, this means that a thread is non-preemptible
if the bundled value is greater than or equal to 0x0080. This is the
only thing the interrupt exit code has to check to decide to try a
reschedule or not.
Change-Id: I902d36c14859d0d7a951a6aa1bea164613821aca
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Some thread fields were 32-bit wide, when they are not even close to
using that full range of values. They are instead changed to 8-bit fields.
- prio can fit in one byte, limiting the priorities range to -128 to 127
- recursive scheduler locking can be limited to 255; a rollover results
most probably from a logic error
- flags are split into execution flags and thread states; 8 bits is
enough for each of them currently, with at worst two states and four
flags to spare (on x86, on other archs, there are six flags to spare)
Doing this saves 8 bytes per stack. It also sets up an incoming
enhancement when checking if the current thread is preemptible on
interrupt exit.
Change-Id: Ieb5321a5b99f99173b0605dd4a193c3bc7ddabf4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Use least significant bits for common flags and high bits for
arch-specific ones.
Change-Id: I982719de4a24d3588c19a0d30bbe7a27d9a99f13
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
replace include <nanokernel.h> with <kernel.h> everywhere and also fix
any remaining mentions of nanokernel.
Keep the legacy samples/tests as is.
Change-Id: Iac48447bd191e83f21a719c69dc26233216d08dc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Obsolete, replaced by _set_thread_return_value().
Change-Id: I23e9cfc07e43542f0965817edc3552d456fd2ef3
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Also remove mentions of unified kernel in various places in the kernel,
samples and documentation.
Change-Id: Ice43bc73badbe7e14bae40fd6f2a302f6528a77d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Also remove some old cflags referencing directories that do not exist
anymore.
Also replace references to legacy APIs in doxygen documentation of
various functions.
Change-Id: I8fce3d1fe0f4defc44e6eb0ae09a4863e33a39db
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
- does not pull in printk(), for potential footprint gain
- does not pull in k_thread_abort(), for single-threaded systems
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Change-Id: Ibc6a198b81a6cd73117d1e85aa05b92a4501a34d
Some kernel operations, like scheduler locking can be optmized out,
since coop threads lock the scheduler by their very nature. Also, the
interrupt exit path for all architecture does not have to do any
rescheduling, again by the nature of non-preemptible threads.
Change-Id: I270e926df3ce46e11d77270330f2f4b463971763
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
nano_cpu_idle/nano_cpu_atomic_idle were not ported to the unified
kernel, and only the old APIs were available. There was no real impact
since, in the unified kernel, only the idle thread should really be
doing power management. However, with a single-threaded kernel, these
functions can be useful again.
The kernel internals now make use of these APIs instead of the legacy
ones.
Change-Id: Ie8a6396ba378d3ddda27b8dd32fa4711bf53eb36
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The way the ready thread cache was implemented caused it to not always
be "hot", i.e. there could be some misses, which happened when the
cached thread was taken out of the ready queue. When that happened, it
was not replaced immediately, since doing so could mean that the
replacement might not run because the flow could be interrupted and
another thread could take its place. This was the more conservative
approach that insured that moving a thread to the cache would never be
wasted.
However, this caused two problems:
1. The cache could not be refilled until another thread context-switched
in, since there was no thread in the cache to compare priorities
against.
2. Interrupt exit code would always have to call into C to find what
thread to run when the current thread was not coop and did not have the
scheduler locked. Furthermore, it was possible for this code path to
encounter a cold cache and then it had to find out what thread to run
the long way.
To fix this, filling the cache is now more aggressive, i.e. the next
thread to put in the cache is found even in the case the current cached
thread is context-switched out. This ensures the interrupt exit code is
much faster on the slow path. In addition, since finding the next thread
to run is now always "get it from the cache", which is a simple fetch
from memory (_kernel.ready_q.cache), there is no need to call the more
complex C code.
On the ARM FRDM K64F board, this improvement is seen:
Before:
1- Measure time to switch from ISR back to interrupted task
switching time is 215 tcs = 1791 nsec
2- Measure time from ISR to executing a different task (rescheduled)
switch time is 315 tcs = 2625 nsec
After:
1- Measure time to switch from ISR back to interrupted task
switching time is 130 tcs = 1083 nsec
2- Measure time from ISR to executing a different task (rescheduled)
switch time is 225 tcs = 1875 nsec
These are the most dramatic improvements, but most of the numbers
generated by the latency_measure test are improved.
Fixes ZEP-1401.
Change-Id: I2eaac147048b1ec71a93bd0a285e743a39533973
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Also remove NO_METRIC, which is not referenced anywhere anymore.
Change-Id: Ieaedf075af070a13aa3d975fee9b6b332203bfec
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Move _thread_base initialization to _init_thread_base(), remove mention
of "nano" in timeouts init and move timeout init to _init_thread_base().
Initialize all base fields via the _init_thread_base in semaphore groups
code.
Change-Id: I05b70b06261f4776bda6d67f358190428d4a954a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Artifact from microkernel, for handling multiple pending tasks on
nanokernel objects.
Change-Id: I3c2959ea2b87f568736384e6534ce8e275f1098f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Prio should be an int, since values are small integers, not a fixed-size
int32_t. It aligns with the prio parameters of the other APIs.
Stack size should be size_t.
Change-Id: Id29751b86c4ad7a7c2a7ffe446c2a96ae83c77bf
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
When a thread dies, at least print the pointer to it, so we can debug
better.
Change-Id: Ief6bbc0c221e2d5271c240a4b73df16413aa5e22
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
There was a lot of duplication between architectures for the definition
of threads and the "nanokernel" guts. These have been consolidated.
Now, a common file kernel/unified/include/kernel_structs.h holds the
common definitions. Architectures provide two files to complement it:
kernel_arch_data.h and kernel_arch_func.h. The first one contains at
least the struct _thread_arch and struct _kernel_arch data structures,
as well as the struct _callee_saved and struct _caller_saved register
layouts. The second file contains anything that needs what is provided
by the common stuff in kernel_structs.h. Those two files are only meant
to be included in kernel_structs.h in very specific locations.
The thread data structure has been separated into three major parts:
common struct _thread_base and struct k_thread, and arch-specific struct
_thread_arch. The first and third ones are included in the second.
The struct s_NANO data structure has been split into two: common struct
_kernel and arch-specific struct _kernel_arch. The latter is included in
the former.
Offsets files have also changed: nano_offsets.h has been renamed
kernel_offsets.h and is still included by the arch-specific offsets.c.
Also, since the thread and kernel data structures are now made of
sub-structures, offsets have to be added to make up the full offset.
Some of these additions have been consolidated in shorter symbols,
available from kernel/unified/include/offsets_short.h, which includes an
arch-specific offsets_arch_short.h. Most of the code include
offsets_short.h now instead of offsets.h.
Change-Id: I084645cb7e6db8db69aeaaf162963fe157045d5a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Verify the thread priorities are within the bounds when starting a new
thread and when changing the priority of a thread.
Change-Id: I007b3b249e4b80235b6439cbee44cad2f31973bb
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Symbols now use the K_ prefix which is now standard for the
unified kernel. Legacy support for these symbols is retained
to allow existing applications to build successfully.
Change-Id: I3ff12c96f729b535eecc940502892cbaa52526b6
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Adds standard prefix to symbolic option that flags a thread
as essential to system operation.
Change-Id: Ia904a81ce343fdd1cd44caaaeae641d822777f9b
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
They were the same, standardize on the lowercase one.
Change-Id: I8bca080e45f3e0970697d4451e468b9081f96f5f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
With this patch we introduce unified kernel support for NIOS II.
Not all test cases have been ported, but the following command
currently succeeds with 43/43 passing test cases:
$ sanitycheck --arch=nios2 -xKERNEL_TYPE=unified \
--tag=unified_capable
Issue: ZEP-934
Change-Id: Id8effa0369a6a22c4d0a789fa2a8e108af0e0786
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Gets rid of unnecessary THREAD_MONITOR_INIT() macro, to be
consistent with the approach taken by _thread_monitor_exit().
Aligns x86 code with the approach used on other architectures.
Revises the associated comments and removes unnecessary
doxygen tags.
Change-Id: Ied1aebcd476afb82f61862b77264efb8a7dc66c9
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Several platforms utilize a ihex image format. Rather than
duplicating the build bits in everyones makefile, pull it into the
toplevel makefile so we all share it.
Change-Id: I9097b06e7e386a69ce6ab4d4e4d56cc776adfec2
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The toolchain headers included an abstraction for defining symbol
names in assembly context in the situation where we're using a
DOS-style assembler that automatically prepends an underscore to
symbol names.
We aren't. Zephyr is an ELF platform. None of our toolchains do
this. Nothing sets the "TOOL_PREPENDS_UNDERSCORE" macro from within
the project, and it surely isn't an industry standard. Yank it out.
Now we can write assembler labels in natural syntax, and a few other
things fall out to simplify too.
(NOTE: these headers contain assembly code and will fail checkpatch.
That is an expected false positive.)
Change-Id: Ic89e74422b52fe50b3b7306a0347d7a560259581
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Completing the terminology change started with change 4008
by updating the Kconfig files processed to produce the
online documentation, plus header files processed by
doxygen. References to 'platform' are change to 'board'
Change-Id: Id0ed3dc1439a0ea0a4bd19d4904889cf79bec33e
Jira: ZEP-534
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Reflects RAM increase that we get with SDK 0.8.2.
Change-Id: I5d7157834e29bb56864e81fedfb9766d5e4a24f8
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Arches now select whether they want to use the GCC built-ins,
their own assembly implementation, or the generic C code.
At the moment, the SDK compilers only support builtins for ARM
and X86. ZEP-557 opened to investigate further.
Change-Id: I53e411b4967d87f737338379bd482bd653f19422
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is at the expense of code size. The QEMU and MAX10
targets have plenty of space so enable it for these boards,
but leave off by default for others.
Change-Id: I93fdb7db14232727e9953b22490d8869ff3b60e7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The comments for INT_ACTIVE and EXC_ACTIVE now refer to
"executing context ..." for all architectures.
Change-Id: Ib868958639a3b30e1814fcaa4d1f0651d3b2561e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The 16550 will now be the default console device.
Change-Id: I92a6b49984b055e7d5f5c97e5192150be0d5c5c7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We are not using this core build any more. Users should be using
the provided F core instead.
Change-Id: I2b5266273030c1bd355aafa78733b4077848d115
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The code expected r10 to be preserved across the call to the
event logger, which wasn't reasonable given that it is caller-
saved.
Change-Id: I694357ea7ee9b410b93b5a0894e8c38c53127363
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The emulator supports all the integer math instructions and has
the necessary registers for exception debugging.
Change-Id: I55938d9e3a4b9d219f6fee06fe070e860ca71d4b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are necessary to edit the CPU design in QSYS.
These originate from the F core archive supplied by Altera.
Change-Id: Ic03bd8738ae58dc154b5eaef91154fadaa61c491
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This build has support for hardware break/watch points.
Change-Id: Icf8a0d4abc82640eedd8c43322ebecf0ef069974
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Used by ARC, ARM, Nios II. x86 has alternate code done in assembly.
Linker scripts had some alarming comments about data/BSS overlap,
but the beginning of BSS is aligned so this can't happen even if
the end of data isn't.
The common code doesn't use fake pointer values for the number of
words in these sections, don't compute or export them.
Change-Id: I4291c2a6d0222d0a3e95c140deae7539ebab3cc3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We now allow use of -mgpopt=global and -mgpopt=data. The 'global'
option is now the default instead of compiler-default local, expanding
global pointer usage to all small data in the system.
For systems where all RAM is less than 64K, the 'data' option may be
appropriate.
Some fixes had to be made to the system in order to get around some
issues:
* prep_c.c no longer uses fake linker variables to figure out the size
of data or BSS, as these gave the linker fits as it tried to compute
relative addresses to them.
* _k_task_ptr_idle is create by sysgen and placed in a special section.
Any small data in a special section needs to be declared extern
with __attribute__((section)) else the compiler will assume it's in
.sdata.
* same situation with extern references to k_pipe_t (fixed pipe_priv
test)
For legacy applications being ported to Nios II which do things that
freak out global pointer calculation, it can be disabled entirely.
Change-Id: I5eb86ee8aefb8e2fac49c5cdd104ee19cea23f6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
needs to be 0x8000 after .sdata and .sbss sections since
register offsets are 16-bit signed values.
Change-Id: Ia7486d32af81e54a6ebac6be7ec308dfdeafe79e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The caches get initialized on boot and flushed after XIP copy
takes place.
Change-Id: I642a14232835a0cf41e007860f5cdb8a2ade1f50
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Use all available ram, cut in half for simulated RAM/ROM
regions. Some larger test cases did not fit in 64K for
non-XIP case.
Change-Id: I12296286ca7efa5bcc1ceef30486c3fe8976811c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Interrupts and context switches are logged. Since this CPU does not
have a power-saving instruction, it never enters a sleep state so
we do not call _sys_k_event_logger_enter_sleep() from anywhere.
Change-Id: Idcef388e93ffea373446997a0f87e93a4db44331
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Interrupts must always be unlocked when coming out of this function
or execution will never leave _power_save() once entered.
Change-Id: Idda9d9be7cfc576a1072afec38000f63ae262a10
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We are not going to handle unimplemented math instruction
exceptions at runtime. Remove remaining comments and exports
related to this. We don't need to leave a gap in the exception
stack frame for it either.
Change-Id: I4f1f3980a0e43bbf6f2f7488a9182f7acb06be05
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Before we were hard-coding them in the assembly file. Makes it
easier to alter the layout of the struct.
Change-Id: I619dc67c68ff87fe60de429a69b2f604292d270c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The faulting instruction was off by 4 bytes and we weren't printing
the exception cause code properly.
Change-Id: I86f4320c7be43dca96940186def56aa5e47bc49f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We want to pass along the stack pointer, not dereference it.
Change-Id: I554eff316bffe50654942746e7960b561abb413b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Pulled from the ARC implementation. Tested via
test_obj_tracing.
Change-Id: I858e89cc9187f99539b362ade8098b3606d31464
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The extra and redundant -serial was casuing issues, remove.
Pass -nographic to work around issues with the experimental QEMU
builds.
Change-Id: I3102fe026a56781d5c4fb20acaa519af368f8a41
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Unnecessary and generates build errors for microkernel.
Change-Id: I678f44aa2b68c8f8954c78e7828e534f0c1f4215
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It's all RAM, but we pretend the range 0x410000 - 0x420000
is the "ROM" region, and stuff gets copied into RAM starting
at 0x400000.
Change-Id: Idf6bd603e2552593f588cf6130ee4da946bcf5a3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Nios II CPUs vary in configuration on whether they support
'mul', 'mulx', and 'div' family of instructions. The compiler
can be told to use GCC integer library routines instead if
needed.
Ideally we would just pull the configuration out of system.h,
but pulling include file #defines into the Make environment
will involve some build system work that is best left to a
later improvement.
We've decided to take this build-time approach rather than
handle unimplemented instruction exceptions, so remove the
hook in exception.S
Change-Id: I05be0d5ed4c1a49b23dca1550ee66fd5891044d2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
If the CPU lacks certain features the only writable bit in the
status register is the PIE bit, so just write the saved value back.
Change-Id: I91537ff640aa9977d19587c4b0ae414028752341
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
No longer necessary as all the stubs which didn't use their
parameters have now been implemented.
Change-Id: I0ab3f024431426fbdac6d17de21e9c7338879f6e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The return value of _Swap() is often treated as a "don't care" value and thus
often ignored. However, there are cases when it is desirable to have a
meaningful return value. This meaningful value can be assigned via
fiberRtnValueSet(). To that end, a new field has been added to the coop
register struct to store this value for when _Swap() needs to return that
meaningful value.
Change-Id: Ic4967fa7d602850c09ebde18e8bfd4c97cda9ec8
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
For this implementation, the presence of a value in global
_offload_routine signifies to the exception code that we should
enter the IRQ handling code even if there are no bits enabled
in ipending. The 'trap' instruction gets us into the exception
handling code.
Change-Id: Iac96adba0eaf24b54ac28678a31c26517867a4d2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We check to see if the stack pointer is somwhere on the
interrupt stack.
Change-Id: Ic9d21e9f03476b9c8955c44cbfa2e61dd1daed22
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Required by microkernel, currently does nothing.
Change-Id: I256886e3a52817d9216599bbf5691bc27c1d0ad8
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Per Altera these files for the /F core are freely distributable.
README included with instructions and links to necessary software.
Origin: Altera
Change-Id: I58c0dbcb5a2b11f0845d4e390e6aa0020d8b3ed5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is a workaround until we can modify the kernel to pull this
value out of system.h instead of Kconfig.
Change-Id: Iaafa9003d2bbcb5b38a050c371466a206f716ae7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Supports Internal Interrupt Controller only for now; EIC
supoort tracked in ZEP-258.
Change-Id: I2d9c5180e61c06b377fce4bda8a59042b68d58f2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
With this code we can successfully boot and context switch into
the main thread. Nanokernel hello_world has the expected
"Hello World!" string in the RAM console.
Change-Id: I56335d992f5a7cbb12d9e4c02d1cc23ea28ae6ef
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
If XIP is turned on, only hardware breakpoints may be used, and
code cannot be loaded onto the device with nios2-download
or GDB 'load' command. RAM-constrained applications are free to
enable this if they need to.
Change-Id: Iee2d41f71f7ca2bc599801cf3cf0fac680273e51
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
When an image is sent over the wire with the GDB 'load' command,
it tries to start execution from the __start symbol, which needs to
be in RAM. Since the reset vector is in ROM, name it something else.
Change-Id: Id0bbfa76db9a8a81bd7ff20be3f2baec81eae15e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Kconfig doesn't enforce any kind of alignment when specifying the
ISR stack size. Perform the assembly equivalent of STACK_ROUND_DOWN.
Change-Id: Ib7fb72ff7db8a3aa20ec6d0c59a03aa8227f6671
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
CONFIG_INIT_STACKS should initialize all stack regions
with 0xaa. Make sure the initial interrupt stack gets this
as well. Take care not to exceed the bounds of the array
if it is not 4-byte aligned.
Change-Id: Ib23329ac84a5a8515272be2944f948e8faba65b3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This core has extra debugging features useful for this bring-up
exercise.
Change-Id: I619bc8768acb1d9be8699a6e238168f47e605f3d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Use a kbuild trick to force built-in.o to get built even if there isn't
any code so we can link properly. This is cleaner than keeping around
empty files that don't do anything.
Change-Id: I4214d21104fe5f49613fa5697c8116b0e8c8aa50
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We get these out of system.h instead. A clause in libc-hooks.c
for newlib added since we don't get RAM size from
CONFIG_SRAM_BASE_ADDRESS.
Change-Id: Ic35113395b951f625e8e29658afe19c525037964
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We will require 6 variables to be defined by SOC-specific
linker script; these values in turn can be pulled from
defines in layout.h.
To help position code correctly we define two new ELF sections
for this arch, 'reset' and 'exceptions'.
Change-Id: Idffbd53895945b7d0ec0aac281e5bf7c85b4b2c2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Nios II does not have a power saving instruction, so there is nothing
to really do here other than ensure that interrupts are in the correct
state when leaving nano_cpu_atomic_idle().
Change-Id: I664c7542dc2fc1795a453d35e183a737dcb20c38
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
For the moment, NIOS2_CPU_SOF must be set with the path to the
CPU configuration. We are checking with Altera on whether we
can directly check in the binary to the source tree.
These scripts depend on tools provided by the Altera Quartus
Prime Lite Edition. This is available for free but requires
registration on Altera's website to obtain.
Change-Id: Ia6cb6c9e43c3e141807a887cb25c47b370a7d8e9
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Altera tools for creating .pof files for flashing onto their
FPGAs require UFM data to be in this special format. Extend
the current 'all' and 'zephyr' targets to additionally create
this .hex file using objcopy, with the same exclusions as the
existing rule for .bin files.
Change-Id: I75293fba47536545359f817a1f2c1ae905b9d25c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
__start is the CPU's reset vector. In a typical Nios II configuration,
the exception vector is 0x20 bytes after the reset vector, severely
constraining the amount of code that can go in here.
Split this into __start and __text_start. The only thing that __start
really need to do is init the instruction cache and jump into
__text_start.
JIRA IDs placed in comments for missing items.
Change-Id: I3c6b8ed65e8fcf6b6a735b80cf007d0180599230
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Linker scripts for Nios II will also need these headers as it
specifies the device's physical layout and various important
vector addresses.
Change-Id: Ie9efaf19e53d2493eed7b9783052393d7ea9dd0f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Introduce a soc-cflags, soc-cxxflags, and soc-aflags as a means for
SoC specific compiler flags to be set without manipulating Kbuild
options directly.
Change-Id: I2c8f5019fb237429e59717ef96bd4251a61dc1a5
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now matches kernel/nanokernel/include/nano_internal.h.
Change-Id: I4dbbf50aa05c55de42100a6896fe0fa3b26955ec
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
BSP builds for Nios II generate a linker.h and system.h which reflects
the configuration for that CPU. This can vary depending on how the CPU
is wired up in QSYS, so it needs to be at the SOC level--we essentially
treat any given CPU configuration as a SOC in Zephyr build terms.
Include these files from <arch/cpu.h>.
Change-Id: I12f76600107fec1a14a2f9cb82b0f55915ec03a6
Origin: Altera Quartus tools, machine generated
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
ZEP-252 will handle implementation of the code here.
Change-Id: I3e9a6c7cdf2d5a3b0240317b772628fead528095
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
At the moment this just jumps into prep_c, with comments left
on other things that need to be done. Having this here ensures that
the early boot code isn't discarded by gc-sections.
vector_table.c removed, it isn't the right approach for this CPU.
Proper method for initializing reset and exception vectors still
being investigated.
Change-Id: Id7965c671f1a55c42ecfb65119497405a646bec4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Avoids confusion with .gitignore rules, which were inadequate to
cover all the places where these files are found. At least in
VIM, these files are now syntax highlighted correctly.
Change-Id: I23810b0ed34129320cc2760e19ed1a610afe039e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are for any Nios II at this stage of bring-up.
Change-Id: Ie4d0c80df164f81f6615ac35d3f42235b04870f1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Basic build framework for Nios2. Everything is stubbed out,
we just want to have a build going so that we can start to
parallelize implementation tasks.
This patch is not intended to be functional, but should be
able to produce a binary for all the nanokernel-based
sanity checks.
Change-Id: I12dd8ca4a2273f7662bee46175822c9bbd99202a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>