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41161 commits

Author SHA1 Message Date
Stephanos Ioannidis
685bf54829 soc: arm: qemu_cortex_a53: Use the refactored AArch64 interrupt system
This commit updates the `qemu_cortex_a53` platform to use the
refactored AArch64 interrupt system.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-03-13 09:59:59 +01:00
Stephanos Ioannidis
91ceee782f arch: arm: aarch64: Refactor interrupt interface
The current AArch64 interrupt system relies on the multi-level
interrupt mechanism and the `irq_nextlevel` public interface to invoke
the Generic Interrupt Controller (GIC) driver functions.

Since the GIC driver has been refactored to provide a direct interface,
in order to resolve various implementation issues described in the GIC
driver refactoring commit, the architecture interrupt control functions
are updated to directly invoke the GIC driver functions.

This commit also adds support for the ARMv8 cores (e.g. Cortex-A53)
that allow interfacing to a custom external interrupt controller
(i.e. non-GIC) by mapping the architecture interrupt control functions
to the SoC layer interrupt control functions when
`ARM_CUSTOM_INTERRUPT_CONTROLLER` configuration is enabled.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-03-13 09:59:59 +01:00
Stephanos Ioannidis
5ac617c817 soc: arm: xilinx_zynqmp: Use the refactored AArch32 interrupt system
This commit updates the `xilinx_zynqmp` platform to use the refactored
AArch32 interrupt system.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-03-13 09:59:59 +01:00
Stephanos Ioannidis
2c5ca5505c arch: arm: aarch32: Refactor interrupt interface
The current AArch32 (Cortex-R and to-be-added Cortex-A) interrupt
system relies on the multi-level interrupt mechanism and the
`irq_nextlevel` public interface to invoke the Generic Interrupt
Controller (GIC) driver functions.

Since the GIC driver has been refactored to provide a direct interface,
in order to resolve various implementation issues described in the GIC
driver refactoring commit, the architecture interrupt control functions
are updated to directly invoke the GIC driver functions.

This commit also adds support for the Cortex-R cores (Cortex-R4 and R5)
that allow interfacing to a custom external interrupt controller
(i.e. non-GIC) by introducing the `ARM_CUSTOM_INTERRUPT_CONTROLLER`
configuration that maps the architecture interrupt control functions to
the SoC layer interrupt control functions.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-03-13 09:59:59 +01:00
Stephanos Ioannidis
5ab698bd56 arch: arm: aarch32: Fix header description
This commit fixes incorrect header descriptions for the ARM AArch32
public headers.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-03-13 09:59:59 +01:00
Stephanos Ioannidis
50519ce7ba interrupt_controller: gic: Refactor GIC driver interface
The current Generic Interrupt Controller (GIC) driver makes use of the
multi-level interrupt mechanism and `irq_nextlevel` public interface.

This is a less-than-ideal implementation for the following reasons:

1. The GIC is often used as the main interrupt controller for the
  Cortex-A and Cortex-R family SoCs and, in this case, it is not a 2nd
  level interrupt controller; in fact, it is the root interrupt
  controller and therefore should be treated as such.

2. The only reason for using `irq_nextlevel` here is to interface the
  architecture implementation to the interrupt controller functions.
  Since there is no nesting or multiple instances of an interrupt
  controller involved, there is really no point in adding such an
  abstraction.

3. 2nd level topology adds many unnecessary abstractions and results
  in strange coding artefacts as well as performance penalty due to
  additional branching.

This commit refactors the GIC driver interface as follows:

1. Remove the current GIC driver interface based on the multi-level
  interrupt mechanism and the `irq_nextlevel` public interface.

2. Define the GIC driver interface in
  `include/drivers/interrupt_controller/gic.h` and allow the arch
  implementation to directly invoke this interface.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-03-13 09:59:59 +01:00
Marcin Niestroj
67527ce4b7 tests: mqtt_packet: use MQTT_UTF8_LITERAL() to simplify code
Using MQTT_UTF8_LITERAL() allows to reduce code and make it less error
prone, since utf8 length is calculated automatically by the macro.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2020-03-13 10:06:18 +02:00
Marcin Niestroj
c0b50c72be net: mqtt: use MQTT_UTF8_LITERAL() to simplify code and fix debug log
Contents of mqtt_3_1_0_proto_desc and mqtt_3_1_1_proto_desc were logged
with following code:

  MQTT_TRC("Encoding Protocol Description. Str:%s Size:%08x.",
           mqtt_proto_desc->utf8, mqtt_proto_desc->size);

This resulted in invalid log, since they were not NULL-terminated
strings. Use MQTT_UTF8_LITERAL() to initialize both utf8 strings to make
sure they are NULL-terminated now and valid to print and
log. Additionally this makes the code a bit shorter.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2020-03-13 10:06:18 +02:00
Marcin Niestroj
accef325a2 net: mqtt: add MQTT_UTF8_LITERAL() helper macro
This macro allows to easily initialize utf8 strings (struct mqtt_utf8)
from C literals, as it automatically calculates string length.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2020-03-13 10:06:18 +02:00
Vincent Wan
c58d8fcb79 soc: ti_simplelink: system power management for cc13x2_cc26x2
Add support for sleep states. Sleep state 1 corresponds to idle mode,
and Sleep state 2 corresponds to standby mode, as per the Technical
Reference Manual.

Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
2020-03-12 19:22:53 -06:00
Vincent Wan
5637def2b3 power: policy: add PM policy function for TI CC13X2/CC26X2
Create a residency-based system power policy function for TI
CC13X2/CC26X2 that uses TI's Power module.

Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
2020-03-12 19:22:53 -06:00
Jose Alberto Meza
7a237649c7 samples: drivers: espi: Check response for OOB transaction
Check OOB response data after OOB transaction over eSPI.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2020-03-13 01:45:18 +02:00
Jose Alberto Meza
b803b32541 drivers: espi: Obtain correct Rx lenght during OOB transaction.
MEC15xx eSPI OOB RX length register holds received message length
and receive buffer length, need to extract rcvd msg length.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2020-03-13 01:45:18 +02:00
Jose Alberto Meza
8b14807e55 samples: boards: mec15xxevb: Power management tests
Sample code that demonstrates power management features on
MEC15xx-based boards.
It showcases how an app can  enter into light and deep sleep.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2020-03-12 23:24:30 +02:00
Anas Nashif
2215d21104 doc: fix broken links in README and board docs
Point to zephyr/sdk release pages instead of non-existent downloads page
on project website.

Fixes #21706

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-03-12 17:18:49 -04:00
Andrzej Głąbek
a6f15d9fd5 boards: nrf: Indicate spi as supported on Nordic DK boards
tests/drivers/spi/spi_loopback provides configurations for boards
nrf51_pca10028 and nrf52840_pca10056, thus indicate spi as supported
on them, so that they are included in sanitycheck builds of this test.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-03-12 15:08:53 -05:00
Andrzej Głąbek
ff01e2a553 samples/bluetooth/hci_spi: Add configuration for nrf51_pca10028
This sample has nrf51_pca10028 on its platform_whitelist but lacks
configuration and overlay files that would make it possible to build
this sample for that board. This commit provides such files.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-03-12 15:08:53 -05:00
Andrzej Głąbek
1a1d8e797b tests/drivers/spi/spi_loopback: Fix configurations for nRF boards
Since commit 22326f6d99 got in, this test
requires that so-called NOP frames (bytes of value 0) are sent when no
TX data is provided. For nRF SoCs, the over-read character (ORC) that
is sent in such case is by default configured to the value of 0xFF.
Alter configurations for nRF boards so that 0x00 is used instead.

On the occasion, remove redundant selections of driver type in those
configurations (CONFIG_SPI_x_NRF_SPI[M]=y), as such selections must
be aligned with the value of "compatible" property in corresponding
nodes in dts, so there's no much sense in having them separately here.

Correct also the SPI instance to be used for nrf51_pca10028.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-03-12 15:08:53 -05:00
Jukka Rissanen
f53d9756be board: arm: black_f407ve: Initial support
Add support for black_f407ve board which is based on
stm32f407xx soc.

Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
2020-03-12 20:18:39 +02:00
Jukka Rissanen
989c6935f2 dts: arm: st: Add stm32f407Xe.dtsi
Add DTS for stm32f407Xe SOC.

Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
2020-03-12 20:18:39 +02:00
Jukka Rissanen
0f1700a08b soc: arm: st_stm32: Add STM32F407XE
Add support for the STM32F407XE SoC.

Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
2020-03-12 20:18:39 +02:00
Ioannis Glaropoulos
d9a6e1d0c0 arch: arm: aarch32: rename z_arm_int_lib_init() function
We rename the z_arm_int_lib_init() function to
z_arm_interrupt_init(), aligning to how other
ARCHes name their IRQ initialization function.
There is nothing about 'library' in this
functionality, so we remove the 'lib' in-fix.

The commit does not introduce any behavior changes.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-03-12 20:11:44 +02:00
Flavio Ceolin
b0b320b7dd drivers: i2c: Remove invalid syscalls
i2c_slave_register/unregister must not be syscalls since it provides
callbacks that will run in supervisor mode. Nonetheless, verification
functions were missing which means that these functions never worked
from usermode.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2020-03-12 19:52:01 +02:00
Wayne Ren
649c678e3b tests: openocd tracing does not support SMP
current openocd tracing does not support SMP

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2020-03-12 13:02:17 -04:00
Wayne Ren
9544350832 arch: arc: fake exception should set not clrear AE bit
To make a fake exception, we should set not clear AE bit

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2020-03-12 13:02:17 -04:00
Wayne Ren
8975c0a33e arch: arc: the stack checking should consider the case of SMP
the old codes just work for single core, we need to consider
the case of SMP.

In SMP, it's not easy to get current thread of current cpu in
assembly, so we'd better do it in C.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2020-03-12 13:02:17 -04:00
Wayne Ren
ea0431d305 arch: arc: fix the trace of isr enter and exit
fix the trace of isr enter and exit

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2020-03-12 13:02:17 -04:00
Wayne Ren
84cdfa271d arch : arc: clean up of assembly codes
* update comments to match latest codes
* add extra comments for some assembly, macros
* use macro to replace duplcated codes
* remove unused codes, lables, symobols

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2020-03-12 13:02:17 -04:00
Wayne Ren
3f88ddd549 arch: arc: overhaul the thread switch code in epilogue of irq and exception
overhaul the thread switch code in epilogue of irq and
exception handling:
* add z_arch_get_next_switch_handle to call z_get_next_switch_handle,
  let the scheduler to decide the switch thread. This will also cover
  the case of SMP.

* put lots of common codes in macros for thread switch to improve
  the maintainablity, readability.

* clean up of some lables to make codes easier to understand

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2020-03-12 13:02:17 -04:00
Wayne Ren
34b033d41d arch: arc: fix the bug of "wait for switch" sychronization
after applying commit 3235451880, arc's arch_switch also need's
corresponding fix.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2020-03-12 13:02:17 -04:00
Wayne Ren
3ae7c87eb0 tests: the arc issuse is fixed
the arc issue is fixed, remove the filter

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2020-03-12 13:02:17 -04:00
Wayne Ren
8e653fe6b1 boards: arc: enable smp by default for multicore targets
hsdk and nsim_hs_smp are multicore targetes, enable smp
by default

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2020-03-12 13:02:17 -04:00
Wayne Ren
f700022a35 arch: arc: bug fixes for running just one core for a multicore target
for smp target, there is a case where just one core is running, then:
* during init, the master core will run, others cores will halt/sleep
* use timer driver for single core

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2020-03-12 13:02:17 -04:00
Markus Fuchs
5f197b6c52 drivers: crypto: stm32: Add CAP_NO_IV_PREFIX capability
Add CAP_NO_IV_PREFIX capability support to the STM32 CRYP crypto driver,
so the initialization vector does not have to be prefixed to the
plaintext/ciphertext buffer.

Signed-off-by: Markus Fuchs <markus.fuchs@de.sauter-bc.com>
2020-03-12 17:52:46 +01:00
George Stefan
350dc0601d boards: riscv: rv32m1_vega: remove no power-save limitation
Now the VEGABoard BLE supports power-saving,
so the docs need to be updated accordingly.

Signed-off-by: George Stefan <george.stefan@nxp.com>
2020-03-12 17:05:02 +02:00
George Stefan
76b1f03345 bluetooth: controller: openisa/RV32M1: use DSM from LLL
Added the functions to turn on/off the radio from LLL.
Added WAKE_IRQ to start radio after it's out of DSM.

Signed-off-by: George Stefan <george.stefan@nxp.com>
2020-03-12 17:05:02 +02:00
Ionut Ursescu
27878377b2 bluetooth: controller: openisa/RV32M1: introducing radio Deep Sleep Mode
Added the functions to turn on/off the radio.
Deep Sleep Mode (DSM)

Signed-off-by: Ionut Ursescu <ionut.ursescu@nxp.com>
Signed-off-by: George Stefan <george.stefan@nxp.com>
2020-03-12 17:05:02 +02:00
Andrew Boie
5a2619e17a kernel: use z_swap_unlocked in k_thread_abort
z_swap_unlocked() does the same construction of using a
dummy spinlock; just use that and make the code simpler.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-03-12 10:57:02 -04:00
Andrew Boie
60be4eb653 kernel: remove comment in k_thread_abort()
z_reschedule_unlocked() is a no-op if the caller is
cooperative, because the logic that maintains the ready queue
ensures that the co-op thread is always at the front unless
some special handling is done like in k_yield(), which does
not happen here.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-03-12 10:57:02 -04:00
Alexander Wachter
79ed6a7e53 drivers: can: loopback: Use thread to send frames.
The loopback driver is a simple driver that can be used to
test CAN subsystems. The actual implementation sends frames
in the same thread that calls the send function.
Some libraries have problems with that behavior.
This PR implements a dedicated thread that calls the callback
for the receiving functions and a msgq in between the sender
and the TX thread.

Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
2020-03-12 16:10:09 +02:00
Pooja Karanjekar
173f636426 soc: silabs_exx32: Make HFRCO frequency configurable
This commit adds an option to configure the frequency
in Hz for the HFRCO clock source. The default value
for this option is 0 which skips the configuration of the HFRCO.
This feature is supported for efm32gg, efm32jg, efm32pg, efm32fg
and efm32mg SOCs currently.

Signed-off-by: Pooja Karanjekar <pooja.karanjekar@lemonbeat.com>
2020-03-12 09:00:21 -05:00
Andrzej Głąbek
2b2a3b030f drivers: spi: nrfx: Prevent double nrfx_spi[m]_uninit calls
Attempt to deinitialize an nrfx driver that is not initialized results
in an assertion failure reported by the driver. And such attempt could
happen in SPI shims when the power state was switched between states
other than ACTIVE.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-03-12 08:57:14 -05:00
Andrei Emeltchenko
767d1bb6f9 logging: log_backend_rb: Use int for memory area size
Change "hex" to "int" for LOG_BACKEND_RB_MEM_SIZE.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2020-03-12 13:31:24 +02:00
Andrei Emeltchenko
dbf1d5d87d logging: log_backend_rb: Make message buffer size configurable
Make slot size configurable making it easy to use with other
platforms.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2020-03-12 13:31:24 +02:00
Andrei Emeltchenko
f4357837af logging: Make ring buffer backend more general
Ring buffer in memory backend does not depends on xtensa adsp board,
so make it general: remove to log_backend_rb and remove dependency on
up_squared_adsp.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2020-03-12 13:31:24 +02:00
Philémon Jaermann
73ae0d8410 driver: sensor: Add i2c_label and i2c_addr in the max30101_config struct
Set the label and addr from the device tree.

Signed-off-by: Philémon Jaermann <p.jaermann@gmail.com>
2020-03-12 13:12:35 +02:00
Alex Porosanu
f39df4c5d4 boards: riscv: rv32m1_vega: remove BLE 2Mbps limitation
Now the VEGABoard BLE support includes the support for
the 2 Mbps BLE PHY, so the docs need to be updated
accordingly.

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
2020-03-12 13:10:04 +02:00
Alex Porosanu
cf96a0bdaa bluetooth: controller: enable 2Mbps PHY for RV32M1
This patch adds the selection of  the necessary CONFIG_*
options for allowing the use of the 2Mbps BLE PHY on
VEGA platform.

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
2020-03-12 13:10:04 +02:00
Alex Porosanu
cb0a6c2eff bluetooth: controller: openisa/RV32M1: add 2 Mbps PHY support
The radio on the VEGA platform supports both 1Mbps, as well
as 2Mbps BLE PHYs. It does not support coded BLE PHY. This patch
adds the necessary callback, as well as timings to enable the 2 Mbps
PHY support in the SW LL HAL for VEGA.

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
2020-03-12 13:10:04 +02:00
Kumar Gala
256c9acace drivers: serial: stellaris: convert to DT_INST defines
Convert driver to use DT_INST_ defines.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-12 04:54:04 -06:00