arch: arc: bug fixes for running just one core for a multicore target
for smp target, there is a case where just one core is running, then: * during init, the master core will run, others cores will halt/sleep * use timer driver for single core Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
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5f197b6c52
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f700022a35
2 changed files with 14 additions and 9 deletions
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@ -126,7 +126,7 @@ done_cache_invalidate:
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jl @_sys_resume_from_deep_sleep
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#endif
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#if CONFIG_MP_NUM_CPUS > 1
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#if defined(CONFIG_SMP) || CONFIG_MP_NUM_CPUS > 1
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_get_cpu_id r0
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breq r0, 0, _master_core_startup
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@ -134,6 +134,9 @@ done_cache_invalidate:
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* Non-masters wait for master core (core 0) to boot enough
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*/
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_slave_core_wait:
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#if CONFIG_MP_NUM_CPUS == 1
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kflag 1
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#endif
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ld r1, [arc_cpu_wake_flag]
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brne r0, r1, _slave_core_wait
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@ -49,10 +49,12 @@
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#define TICKLESS (IS_ENABLED(CONFIG_TICKLESS_KERNEL))
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#define SMP_TIMER_DRIVER (CONFIG_SMP && CONFIG_MP_NUM_CPUS > 1)
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static struct k_spinlock lock;
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#ifdef CONFIG_SMP
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#if SMP_TIMER_DRIVER
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volatile static u64_t last_time;
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volatile static u64_t start_time;
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@ -128,7 +130,7 @@ static ALWAYS_INLINE void timer0_limit_register_set(u32_t count)
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z_arc_v2_aux_reg_write(_ARC_V2_TMR0_LIMIT, count);
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}
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#ifndef CONFIG_SMP
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#if !SMP_TIMER_DRIVER
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static u32_t elapsed(void)
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{
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u32_t val, ov, ctrl;
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@ -161,7 +163,7 @@ static void timer_int_handler(void *unused)
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/* clear the interrupt by writing 0 to IP bit of the control register */
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timer0_control_register_set(_ARC_V2_TMR_CTRL_NH | _ARC_V2_TMR_CTRL_IE);
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#ifdef CONFIG_SMP
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#if defined(CONFIG_SMP) && CONFIG_MP_NUM_CPUS > 1
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u64_t curr_time;
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k_spinlock_key_t key;
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@ -200,7 +202,7 @@ int z_clock_driver_init(struct device *device)
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/* ensure that the timer will not generate interrupts */
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timer0_control_register_set(0);
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#ifdef CONFIG_SMP
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#if SMP_TIMER_DRIVER
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IRQ_CONNECT(IRQ_TIMER0, CONFIG_ARCV2_TIMER_IRQ_PRIORITY,
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timer_int_handler, NULL, 0);
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@ -234,7 +236,7 @@ void z_clock_set_timeout(s32_t ticks, bool idle)
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* then shut off the counter. (Note: we can assume if idle==true
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* that interrupts are already disabled)
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*/
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#ifdef CONFIG_SMP
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#if SMP_TIMER_DRIVER
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/* as 64-bits GFRC is used as wall clock, it's ok to ignore idle
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* systick will not be missed.
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* However for single core using 32-bits arc timer, idle cannot
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@ -313,7 +315,7 @@ u32_t z_clock_elapsed(void)
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u32_t cyc;
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k_spinlock_key_t key = k_spin_lock(&lock);
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#ifdef CONFIG_SMP
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#if SMP_TIMER_DRIVER
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cyc = (z_arc_connect_gfrc_read() - last_time) / CYC_PER_TICK;
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#else
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cyc = elapsed() / CYC_PER_TICK;
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@ -326,7 +328,7 @@ u32_t z_clock_elapsed(void)
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u32_t z_timer_cycle_get_32(void)
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{
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#ifdef CONFIG_SMP
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#if SMP_TIMER_DRIVER
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return z_arc_connect_gfrc_read() - start_time;
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#else
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k_spinlock_key_t key = k_spin_lock(&lock);
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@ -366,7 +368,7 @@ void sys_clock_disable(void)
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}
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#ifdef CONFIG_SMP
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#if SMP_TIMER_DRIVER
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void smp_timer_init(void)
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{
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/* set the initial status of timer0 of each slave core
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