Modify the gen_isr_table test case to using ztest. Although it was
split up to three test cases, the test logic and the tested platform
are totally the same as previous one.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
The gen_isr_table test now tries to install two dynamic
IRQ handlers.
RISCV32 has a workaround due to limited number of SW
triggerable interrupts that can be configured.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
So far, only implemented on ARM.
It's not possible to do this on Nios II and RISC-V.
Change-Id: I84c8d99cd163dff46de4bc4a7ae40768daf8e4ce
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This test is intended to verify that the SW ISR and vector tables
have been populated correctly.
Change-Id: Ic7f50c02dc0807d7ddefa710da67f818ff707ad6
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
