Add an additional option to the spi_cs_control struct that records how
the pin has been configured in devicetree. For drivers that are not
updated, the CS behaviour is the same as before (Push-Pull).
Use the devicetree knowledge with the GPIO subsystem so that the correct
physical pin levels for the CS pin are automatically selected.
Fixes#26267
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add Nuvoton numicro series UART support, currently supports
only poll mode.
UART0 clock and pincontrol are directly configured, will be
replace when clock and gpio support is added.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Add initial support for nuvoton numicro m48x SoC series, basic
init and uart functionality are covered with gpio and clock
directly relies on HAL.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
PCIe shell was enabled by default if shell is enabled in below commit:
commit ee985d81aa ("shell: enable modules by default if shell is
enabled").
However, this shell file has tests for PCIe RC, not applicable to EP.
So, should not be default enabled for PCIe EP.
If we add EP shell tests in future, they should be added under
drivers/pcie/endpoint/ directory.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add devicetree overlay for connecting an Mikroe ADC click shield to an
NXP LPCXpresso55S16 development board.
The LPCXpresso55S16 uses SSEL1 (CS1) for mikroBUS SPI, whereas the
generic Mikroe ADC click board definition assumes SPI CS0.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Use the recently introduced mikrobus_spi devicetree node as parent node
instead of relying on mapping for arduino_spi.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
The Seeeduino XIAO is a tiny (20 mm x 17.5 mm) ARM development
board with onboard LEDs, USB port, and range of I/O broken out
onto 14 pins.
Signed-off-by: Michael Hope <mlhx@google.com>
Fixes whitespace in the frdm_kw41z shield document to allow continuation
in the numbered list of Bluetooth controller instructions and to format
the jumper configuration sublist correctly.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This enables PWM and connects it to the main LED. Tested by running
samples/basic/blinky_pwm and /fade_led.
Signed-off-by: Michael Hope <mlhx@google.com>
This runs the Timer/Counter for Control in 'normal' PWM mode. The
number of channels and counter width depends on the device and is
imported from DeviceTree.
Signed-off-by: Michael Hope <mlhx@google.com>
The SAMD21 series has three timer/counters with a mix of channels and
resolutions. Note that the SAMD20 only has TC peripherals and no TCC
peripherals which is why the changes are in samd21.dtsi.
Signed-off-by: Michael Hope <mlhx@google.com>
The SAM0 Timer/Counter for Control Applications can act as a counter
or generator. Add a binding for the TCC in PWM mode and helper to
check the compat mode.
Signed-off-by: Michael Hope <mlhx@google.com>
Fixes#26413.
The devicetree for disco_l475_iot1 declares the flash partitions
"storage" and "image-scratch" with overlapping address spaces.
As a result, when one of these partitions is used it can corrupt the
contents of the other one. This is the case when mcuboot performs an
image swap using the scratch partition.
To fix the bug, the size of the scratch partition is reduced.
Signed-off-by: Hans Wilmers <hans@wilmers.no>
In this board DT the "storage" and "image-scratch" are declared
with overlapping address spaces.
As a result, when one of these partitions is used it can corrupt the
contents of the other one. This is the case when mcuboot performs an
image swap using the scratch partition.
To fix the bug, the size of the scratch partition is reduced.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Use '0xa0' as default priority to be consistent with the V1/V2 and
V3 drivers default priority init.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
GICC_BPR has minimum legal values in secure and non-secure states.
'3' is the minimum BPR value leading to group and sub-group priority
as 'gggg.ssss'. In order to make an IRQ preemptible they need to
be in different priority group.
Hence to be generic priority values should be above '0x0f'.
IRQ0 - default priority (low prio)
IRQ1 - 0x0 (highest prio)
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Add api to raise SGI to target cores in affinity level identified
by MPIDR. Currently only EL1S is supported.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
This commit creates a list of a phony targets for each runner, that is:
`west_flash_depends`, `west_debug_depends`, and so on.
Those targets has identical dependencies as CMake runner target.
flash, debug, debugserver, attach targets.
As example `ninja flash` correctly ensures dependencies are taken into
consideration before calling `west flash`.
Unfortunately, calling `west flash` directly would not re-run the flash
dependencies, cause `west flash` would only build the default CMake
target.
Now, `west flash` calls the phony `west_flash_depends` target, ensuring
all deps are up-to-date before flashing (unless --skip-rebuild is given)
The same is true for the other mentioned runners.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit renames `FLASH_DEPS` to `RUNNERS_DEPS`.
The current name `FLASH_DEPS` is misleading in the sense that this
depency is added to all runner targets, flash, debug, debugserver,
attach, and not only the flash runners.
Therefore this is now named `RUNNERS_DEPS` instead.
Similar, zephyr_property_target now contains the property
FLASH_DEPENDENCIES, DEBUG_DEPENDENCIES, and so on, so that additional
dependencies can be added for each runner.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
In sys_rand_get() if the entropy hardware unlikely return error, the
fallgback is using the system timer to and fill the given buffer with
that data.
The problem what that k_cycle_get_32() returns a four bytes integer and
depending the sizeof of the buffer we need copy the right amount of
data. That was not being done properly leading to invalid read/write
memory access.
Fixes#26435
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Michael Hope
