The PCI API was originally limited to 32 bit addresses. Even though
it had code to skip over the high word in 64 bit BAR entries, it
refused to use it and returned a 32 bit value. Some devices in the
wild have default mappings from the firmware for devices above 4G.
Also remove the "iobar" API. It's dead code, we don't call it and we
don't test it. IO space BAR entries are a legacy feature from way,
way back in PCI history (I genuinely have never heard of a real device
that uses them!). And there's no difference in format between one of
these and a 32 bit "memory" BAR anyway, someone who actually had this
requirement could just use the existing API without worry.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
PCIe End Point can get three different reset interrupts from the
Root Complex, Function Level Reset (FLR), PCI Express Reset (PERST)
and Inband PCI Express Reset (INB PERST).
Add public API to let PCIe EP drivers register callback function
for each PCIe reset interrupt. This callback function should be
executed from corresponding reset interrupt handler if registered.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Introduce common API to achieve data transfer using memcpy
to/from outbound region of PCIe EP.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add public APIs for PCIe endpoint driver:
- EP configuration space read/write
- Mapping/Unmapping of Host buffer and PCIe outbound region
- Raise interrupt to Host
These are minimal base APIs to make PCIe EP functional.
Also, add a Kconfig and an empty CMakeLists.txt for drivers to extend.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
This trivial patch extends the PCIe shell to check for and report
on a device's ability to use MSI-X interrupt signaling.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Some firmwares (looking at you, slimbootloader) don't set the registers
in PCI configuration space to indicate the IRQ routing, so we remove
the check that verifies that the user and firmware agree on IRQ number.
Also eliminate the return value of pcie_irq_enable() since no one uses
it and we can't return a meaningful value any longer.
Signed-off-by: Charles Youse <charles.youse@intel.com>
Firmware is supposed to set a register in PCI configuration space which
indicates the hardware IRQ that the endpoint is attached to.
A function is implemented which reads this register, and the PCIe shell
is updated to use it instead of doing it "manually".
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
A new function pcie_irq_enable() is added to be used in lieu of
irq_enable() when the target device is PCI(e)-attached. The function
attempts to use MSI, when configured in the kernel and supported by
the endpoint; failing that, it will verify that IRQ requested is in
fact routed to the device by the boot firmware before enabling it.
The NS16550 UART driver is updated to use pcie_irq_enable().
The PCI(e) shell is extended to dump information about wired IRQs.
The up_squared devicetree is fixed (reverted?) to IRQ5 for UART1.
The galileo enables MSI by default.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
