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dts: Remove num-irqs from the arm nvic node

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Move back to getting the number of IRQs from Kconfig.  We do this
because the number of IRQs should really just be determined by scanning
the device tree and figuring out the highest IRQ value used.

Change-Id: I8e0dbec1d9d036d4e899b237c4dc7d833c422e18
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-03-24 15:08:14 -05:00
commit ffd7c9f696
21 changed files with 13 additions and 38 deletions
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8
arch/arm/soc/arm/beetle/Kconfig.defconfig.series
View file

@ -13,16 +13,16 @@ source "arch/arm/soc/arm/beetle/Kconfig.defconfig.beetle*"
config SOC_SERIES config SOC_SERIES
default beetle default beetle
config NUM_IRQS
int
default 45
if !HAS_DTS if !HAS_DTS
config NUM_IRQ_PRIO_BITS config NUM_IRQ_PRIO_BITS
int int
default 3 default 3
config NUM_IRQS
int
default 45
config SRAM_BASE_ADDRESS config SRAM_BASE_ADDRESS
default 0x20000000 default 0x20000000

4
arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.series
View file

@ -23,13 +23,13 @@ config NUM_IRQ_PRIO_BITS
int int
default 4 default 4
endif # !HAS_DTS
config NUM_IRQS config NUM_IRQS
int int
# must be >= the highest interrupt number used # must be >= the highest interrupt number used
default 86 default 86
endif # !HAS_DTS
source "arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.mk*" source "arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.mk*"
endif # SOC_SERIES_KINETIS_K6X endif # SOC_SERIES_KINETIS_K6X

4
arch/arm/soc/nxp_kinetis/kwx/Kconfig.defconfig.mkw41z4
View file

@ -17,12 +17,12 @@ config NUM_IRQ_PRIO_BITS
int int
default 2 default 2
endif # !HAS_DTS
config NUM_IRQS config NUM_IRQS
int int
default 32 default 32
endif # !HAS_DTS
if PINMUX if PINMUX
config PINMUX_MCUX config PINMUX_MCUX

2
arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f103xb
View file

@ -17,11 +17,11 @@ config SRAM_SIZE
config FLASH_SIZE config FLASH_SIZE
default 128 default 128
endif # !HAS_DTS
config NUM_IRQS config NUM_IRQS
int int
default 59 default 59
endif # !HAS_DTS
endif # SOC_STM32F103XB endif # SOC_STM32F103XB

3
arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l476xx
View file

@ -19,10 +19,11 @@ config SRAM_SIZE
config FLASH_SIZE config FLASH_SIZE
default 1024 default 1024
endif # !HAS_DTS
config NUM_IRQS config NUM_IRQS
int int
default 82 default 82
endif # !HAS_DTS
endif # SOC_STM32L476XX endif # SOC_STM32L476XX

4
arch/arm/soc/ti_simplelink/cc32xx/Kconfig.defconfig.cc3200
View file

@ -18,14 +18,14 @@ config SRAM_SIZE
config FLASH_SIZE config FLASH_SIZE
default 0 default 0
endif # !HAS_DTS
config NUM_IRQS config NUM_IRQS
int int
# must be >= the highest interrupt number used # must be >= the highest interrupt number used
# This includes the NWP interrupt # This includes the NWP interrupt
default 179 default 179
endif # !HAS_DTS
config CC3200SDK_LIBRARY config CC3200SDK_LIBRARY
def_bool n def_bool n

1
dts/arm/cc3200_launchxl.fixup
View file

@ -1,4 +1,3 @@
#define CONFIG_NUM_IRQS ARM_ARMV7M_NVIC_E000E100_NUM_IRQS
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS #define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define EXCEPTION_UARTA0 TI_CC32XX_UART_4000C000_IRQ_0 #define EXCEPTION_UARTA0 TI_CC32XX_UART_4000C000_IRQ_0

1
dts/arm/cc32xx_launchxl.dtsi
View file

@ -46,5 +46,4 @@
&nvic { &nvic {
num-irq-prio-bits = <3>; num-irq-prio-bits = <3>;
num-irqs = <179>;
}; };

1
dts/arm/frdm_k64f.fixup
View file

@ -1,4 +1,3 @@
#define CONFIG_NUM_IRQS ARM_ARMV7M_NVIC_E000E100_NUM_IRQS
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS #define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE #define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE

1
dts/arm/frdm_kw41z.fixup
View file

@ -1,4 +1,3 @@
#define CONFIG_NUM_IRQS ARM_ARMV6M_NVIC_E000E100_NUM_IRQS
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV6M_NVIC_E000E100_NUM_IRQ_PRIO_BITS #define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV6M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CONFIG_UART_MCUX_LPUART_0_BAUD_RATE NXP_KW41Z_LPUART_40054000_BAUD_RATE #define CONFIG_UART_MCUX_LPUART_0_BAUD_RATE NXP_KW41Z_LPUART_40054000_BAUD_RATE

1
dts/arm/hexiwear_k64.fixup
View file

@ -1,4 +1,3 @@
#define CONFIG_NUM_IRQS ARM_ARMV7M_NVIC_E000E100_NUM_IRQS
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS #define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE #define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE

2
dts/arm/nucleo_l476rg.fixup
View file

@ -4,8 +4,6 @@
* generated data matches the driver definitions. * generated data matches the driver definitions.
*/ */
#define CONFIG_NUM_IRQS ARM_ARMV7M_NVIC_E000E100_NUM_IRQS
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS #define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS #define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS

1
dts/arm/nxp_k6x.dtsi
View file

@ -271,6 +271,5 @@
}; };
&nvic { &nvic {
num-irqs = <86>;
num-irq-prio-bits = <4>; num-irq-prio-bits = <4>;
}; };

1
dts/arm/nxp_kw41z.dtsi
View file

@ -182,6 +182,5 @@
}; };
&nvic { &nvic {
num-irqs = <32>;
num-irq-prio-bits = <2>; num-irq-prio-bits = <2>;
}; };

1
dts/arm/olimexino_stm32.fixup
View file

@ -5,7 +5,6 @@
*/ */
#define CONFIG_NUM_IRQS ARM_ARMV7M_NVIC_E000E100_NUM_IRQS
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS #define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS #define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS

1
dts/arm/stm32f103xb.dtsi
View file

@ -94,5 +94,4 @@
&nvic { &nvic {
num-irq-prio-bits = <4>; num-irq-prio-bits = <4>;
num-irqs = <59>;
}; };

1
dts/arm/stm32l476.dtsi
View file

@ -126,5 +126,4 @@
&nvic { &nvic {
num-irq-prio-bits = <4>; num-irq-prio-bits = <4>;
num-irqs = <82>;
}; };

1
dts/arm/v2m_beetle.dts
View file

@ -48,5 +48,4 @@
&nvic { &nvic {
num-irq-prio-bits = <3>; num-irq-prio-bits = <3>;
num-irqs = <45>;
}; };

1
dts/arm/v2m_beetle.fixup
View file

@ -1,4 +1,3 @@
#define CONFIG_NUM_IRQS ARM_ARMV7M_NVIC_E000E100_NUM_IRQS
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS #define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CMSDK_APB_UART_0_IRQ ARM_CMSDK_UART_40004000_IRQ_0 #define CMSDK_APB_UART_0_IRQ ARM_CMSDK_UART_40004000_IRQ_0

6
dts/arm/yaml/arm,armv6m-nvic.yaml
View file

@ -24,12 +24,6 @@ properties:
description: number of bits of IRQ priorities description: number of bits of IRQ priorities
generation: define generation: define
- num-irqs:
category: required
type: int
description: number of interrupts controlled by controller
generation: define
cell_string: IRQ cell_string: IRQ
"#cells": "#cells":

6
dts/arm/yaml/arm_cortex_m4_nvic.yaml
View file

@ -24,12 +24,6 @@ properties:
description: number of bits of IRQ priorities description: number of bits of IRQ priorities
generation: define generation: define
- num-irqs:
category: required
type: int
description: number of interrupts controlled by controller
generation: define
cell_string: IRQ cell_string: IRQ
"#cells": "#cells":