modules: hal_silabs: Introduce WiseConnect SDK
WiseConnect SDK is need for Silabs SiWx91x series. Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
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7 changed files with 87 additions and 1 deletions
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@ -1,4 +1,5 @@
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add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_S0 gecko)
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add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_S1 gecko)
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add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_S2 simplicity_sdk)
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add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_SIWX91X wiseconnect)
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add_subdirectory_ifdef(CONFIG_HAS_SILABS_SI32 si32)
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@ -19,6 +19,11 @@ config HAS_SILABS_SISDK
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select HAS_CMSIS_CORE
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depends on SOC_FAMILY_SILABS_S2
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config HAS_SILABS_WISECONNECT
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bool
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select HAS_CMSIS_CORE
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depends on SOC_FAMILY_SILABS_SIWX91X
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config HAS_SILABS_SI32
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bool
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select HAS_CMSIS_CORE
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54
modules/hal_silabs/wiseconnect/CMakeLists.txt
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54
modules/hal_silabs/wiseconnect/CMakeLists.txt
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# Copyright (c) 2024 Silicon Laboratories Inc.
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# SPDX-License-Identifier: Apache-2.0
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set(SISDK_DIR ${ZEPHYR_HAL_SILABS_MODULE_DIR}/simplicity_sdk)
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set(WISECONNECT_DIR ${ZEPHYR_HAL_SILABS_MODULE_DIR}/wiseconnect)
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# Keep these values sync with
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# components/device/silabs/si91x/mcu/core/chip/component/siwg917*.slcc
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zephyr_compile_definitions(
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SL_SI91X_ENABLE_LITTLE_ENDIAN
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SLI_SI91X_MCU_COMMON_FLASH_MODE
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SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2
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SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
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SLI_SI91X_MCU_ENABLE_FLASH_BASED_EXECUTION
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SLI_SI91X_MCU_ENABLE_IPMU_APIS
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SLI_SI91X_MCU_INTERFACE
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SLI_SI917
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SLI_SI917B0
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CLOCK_ROMDRIVER_PRESENT
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)
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zephyr_include_directories(
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${SISDK_DIR}/platform/common/inc
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${SISDK_DIR}/platform/common/config
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/config
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/inc
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/rom_driver/inc
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/systemlevel/inc
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/unified_api/inc
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/cmsis_driver/config
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/cmsis_driver
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include
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)
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zephyr_library_sources(
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${SISDK_DIR}/platform/common/src/sl_core_cortexm.c
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/clock_update.c
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ulpss_clk.c
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/sl_si91x_peripheral_gpio.c
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/ipmu_apis.c
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${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/rsi_system_config_917.c
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)
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zephyr_linker_sources(ROM_SECTIONS linker/code_classification_text.ld)
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zephyr_linker_sources(RAMFUNC_SECTION linker/code_classification_ramfunc.ld)
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@ -0,0 +1,9 @@
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/*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Place data annotated as ramfunc into the Zephyr .ramfunc section.
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*/
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*(text_application_ram)
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@ -0,0 +1,15 @@
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/*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Place text sections tagged with Silicon Labs code classification annotations into flash.
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*/
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SECTION_PROLOGUE(.cc_text,,)
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{
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_cc_text_start = .;
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*(SORT_BY_ALIGNMENT(text_*[0-9]))
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_cc_text_end = .;
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} GROUP_LINK_IN(ROMABLE_REGION)
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_cc_text_size = _cc_text_end - _cc_text_start;
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@ -38,7 +38,9 @@ tests:
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# compatible with C++98.
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# Exclude CONFIG_HAS_RENESAS_RA_FSP and CONFIG_HAS_RENESAS_RZ_FSP as Renesas HALs are not
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# compatible with C++98.
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# Exclude CONFIG_HAS_SILABS_WISECONNECT as Wiseconnect is not compatible with C++98.
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filter: not CONFIG_HAS_RENESAS_RA_FSP and not CONFIG_HAS_RENESAS_RZ_FSP and
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not CONFIG_HAS_SILABS_WISECONNECT and
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not (CONFIG_CPU_CORTEX_M and (CONFIG_NRF_PLATFORM_HALTIUM or CONFIG_SOC_SERIES_NRF54LX))
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build_only: true
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extra_configs:
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2
west.yml
2
west.yml
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@ -228,7 +228,7 @@ manifest:
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groups:
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- hal
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- name: hal_silabs
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revision: df3414d50b321e11b5fb92f76c994aa07141239f
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revision: 2e64a70dbb6396271a8eb8b9ee3f57dc747b5997
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path: modules/hal/silabs
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groups:
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- hal
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