modules: hal_silabs: Introduce WiseConnect SDK

WiseConnect SDK is need for Silabs SiWx91x series.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>

modules/hal_silabs/CMakeLists.txt

@@ -1,4 +1,5 @@
 add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_S0 gecko)
 add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_S1 gecko)
 add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_S2 simplicity_sdk)
+add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_SIWX91X wiseconnect)
 add_subdirectory_ifdef(CONFIG_HAS_SILABS_SI32 si32)

modules/hal_silabs/Kconfig

@@ -19,6 +19,11 @@ config HAS_SILABS_SISDK
 	select HAS_CMSIS_CORE
 	depends on SOC_FAMILY_SILABS_S2
 
+config HAS_SILABS_WISECONNECT
+	bool
+	select HAS_CMSIS_CORE
+	depends on SOC_FAMILY_SILABS_SIWX91X
+
 config HAS_SILABS_SI32
 	bool
 	select HAS_CMSIS_CORE

modules/hal_silabs/wiseconnect/CMakeLists.txt

@@ -0,0 +1,54 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+set(SISDK_DIR ${ZEPHYR_HAL_SILABS_MODULE_DIR}/simplicity_sdk)
+set(WISECONNECT_DIR ${ZEPHYR_HAL_SILABS_MODULE_DIR}/wiseconnect)
+
+# Keep these values sync with
+# components/device/silabs/si91x/mcu/core/chip/component/siwg917*.slcc
+zephyr_compile_definitions(
+  SL_SI91X_ENABLE_LITTLE_ENDIAN
+  SLI_SI91X_MCU_COMMON_FLASH_MODE
+  SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2
+  SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+  SLI_SI91X_MCU_ENABLE_FLASH_BASED_EXECUTION
+  SLI_SI91X_MCU_ENABLE_IPMU_APIS
+  SLI_SI91X_MCU_INTERFACE
+  SLI_SI917
+  SLI_SI917B0
+  CLOCK_ROMDRIVER_PRESENT
+)
+
+zephyr_include_directories(
+  ${SISDK_DIR}/platform/common/inc
+  ${SISDK_DIR}/platform/common/config
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/config
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/inc
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/rom_driver/inc
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/systemlevel/inc
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/unified_api/inc
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/cmsis_driver/config
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/cmsis_driver
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include
+)
+
+zephyr_library_sources(
+  ${SISDK_DIR}/platform/common/src/sl_core_cortexm.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/clock_update.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ulpss_clk.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/sl_si91x_peripheral_gpio.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/ipmu_apis.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/rsi_system_config_917.c
+)
+
+zephyr_linker_sources(ROM_SECTIONS linker/code_classification_text.ld)
+zephyr_linker_sources(RAMFUNC_SECTION linker/code_classification_ramfunc.ld)

modules/hal_silabs/wiseconnect/linker/code_classification_ramfunc.ld

@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Place data annotated as ramfunc into the Zephyr .ramfunc section.
+ */
+
+*(text_application_ram)

modules/hal_silabs/wiseconnect/linker/code_classification_text.ld

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Place text sections tagged with Silicon Labs code classification annotations into flash.
+ */
+
+SECTION_PROLOGUE(.cc_text,,)
+{
+    _cc_text_start = .;
+    *(SORT_BY_ALIGNMENT(text_*[0-9]))
+    _cc_text_end = .;
+} GROUP_LINK_IN(ROMABLE_REGION)
+_cc_text_size = _cc_text_end - _cc_text_start;

tests/lib/cpp/cxx/testcase.yaml

@@ -38,7 +38,9 @@ tests:
     # compatible with C++98.
     # Exclude CONFIG_HAS_RENESAS_RA_FSP and CONFIG_HAS_RENESAS_RZ_FSP as Renesas HALs are not
     # compatible with C++98.
+    # Exclude CONFIG_HAS_SILABS_WISECONNECT as Wiseconnect is not compatible with C++98.
     filter: not CONFIG_HAS_RENESAS_RA_FSP and not CONFIG_HAS_RENESAS_RZ_FSP and
+            not CONFIG_HAS_SILABS_WISECONNECT and
             not (CONFIG_CPU_CORTEX_M and (CONFIG_NRF_PLATFORM_HALTIUM or CONFIG_SOC_SERIES_NRF54LX))
     build_only: true
     extra_configs:

west.yml

@@ -228,7 +228,7 @@ manifest:
       groups:
         - hal
     - name: hal_silabs
-      revision: df3414d50b321e11b5fb92f76c994aa07141239f
+      revision: 2e64a70dbb6396271a8eb8b9ee3f57dc747b5997
       path: modules/hal/silabs
       groups:
         - hal