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dt-bindings: arm: st: add dts support for DMA of some series of stm32

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Add dts support for f0/f1/f2/f3/f4/f7/l0/l4 series STM32.

Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
This commit is contained in:
Song Qiang 2019-10-24 12:34:28 +08:00 • committed by Kumar Gala
commit ff3889a051
14 changed files with 190 additions and 0 deletions
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11
dts/arm/st/f0/stm32f0.dtsi
View file

@ -311,6 +311,17 @@
label = "ADC_1"; label = "ADC_1";
#io-channel-cells = <1>; #io-channel-cells = <1>;
}; };
dma1: dma@40020000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
interrupts = <9 0 10 0 10 0 11 0 11 0>;
st,mem2mem;
status = "disabled";
label = "DMA_1";
};
}; };
}; };

4
dts/arm/st/f0/stm32f072.dtsi
View file

@ -81,6 +81,10 @@
phase-seg1 = <5>; phase-seg1 = <5>;
phase-seg2 = <6>; phase-seg2 = <6>;
}; };
dma1: dma@40020000 {
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
};
}; };
usb_fs_phy: usbphy { usb_fs_phy: usbphy {

16
dts/arm/st/f0/stm32f091.dtsi
View file

@ -52,5 +52,21 @@
label = "GPIOE"; label = "GPIOE";
}; };
}; };
dma1: dma@40020000 {
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
};
dma2: dma@40020400 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020400 0x400>;
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0
11 0 10 0 10 0 11 0 11 0 11 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
}; };
}; };

11
dts/arm/st/f1/stm32f1.dtsi
View file

@ -245,6 +245,17 @@
label = "ADC_1"; label = "ADC_1";
#io-channel-cells = <1>; #io-channel-cells = <1>;
}; };
dma1: dma@40020000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
st,mem2mem;
status = "disabled";
label = "DMA_1";
};
}; };
}; };

11
dts/arm/st/f1/stm32f103Xe.dtsi
View file

@ -134,5 +134,16 @@
#pwm-cells = <2>; #pwm-cells = <2>;
}; };
}; };
dma2: dma@40020400 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = < 56 0 57 0 58 0 59 0 60 0>;
st,mem2mem;
status = "disabled";
label = "DMA_1";
};
}; };
}; };

10
dts/arm/st/f1/stm32f107.dtsi
View file

@ -73,5 +73,15 @@
#pwm-cells = <2>; #pwm-cells = <2>;
}; };
}; };
dma2: dma@40020400 {
compatible = "st,stm32-dma";
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = <56 0 57 0 58 0 59 0 60 0>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
}; };
}; };

21
dts/arm/st/f2/stm32f2.dtsi
View file

@ -232,6 +232,27 @@
label = "ADC_1"; label = "ADC_1";
#io-channel-cells = <1>; #io-channel-cells = <1>;
}; };
dma1: dma@40026000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40026000 0x400>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
status = "disabled";
label = "DMA_1";
};
dma2: dma@40026400 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40026400 0x400>;
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
}; };
otgfs_phy: otgfs_phy { otgfs_phy: otgfs_phy {

11
dts/arm/st/f3/stm32f3.dtsi
View file

@ -316,6 +316,17 @@
label = "ADC_1"; label = "ADC_1";
#io-channel-cells = <1>; #io-channel-cells = <1>;
}; };
dma1: dma@40020000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
st,mem2mem;
status = "disabled";
label = "DMA_1";
};
}; };
usb_fs_phy: usbphy { usb_fs_phy: usbphy {

10
dts/arm/st/f3/stm32f303Xc.dtsi
View file

@ -23,5 +23,15 @@
reg = <0x08000000 DT_SIZE_K(256)>; reg = <0x08000000 DT_SIZE_K(256)>;
}; };
}; };
dma2: dma@40020400 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = <56 0 57 0 58 0 59 0 60 0>;
status = "disabled";
label = "DMA_2";
};
}; };
}; };

10
dts/arm/st/f3/stm32f373Xc.dtsi
View file

@ -18,5 +18,15 @@
reg = <0x08000000 DT_SIZE_K(256)>; reg = <0x08000000 DT_SIZE_K(256)>;
}; };
}; };
dma2: dma@40020400 {
compatible = "st,stm32-dma";
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = <56 0 57 0 58 0 59 0 60 0>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
}; };
}; };

21
dts/arm/st/f4/stm32f4.dtsi
View file

@ -378,6 +378,27 @@
label = "ADC_1"; label = "ADC_1";
#io-channel-cells = <1>; #io-channel-cells = <1>;
}; };
dma1: dma@40026000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40026000 0x400>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
status = "disabled";
label = "DMA_1";
};
dma2: dma@40026400 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40026400 0x400>;
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
}; };
otgfs_phy: otgfs_phy { otgfs_phy: otgfs_phy {

21
dts/arm/st/f7/stm32f7.dtsi
View file

@ -619,6 +619,27 @@
label = "ADC_1"; label = "ADC_1";
#io-channel-cells = <1>; #io-channel-cells = <1>;
}; };
dma1: dma@40026000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40026000 0x400>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
status = "disabled";
label = "DMA_1";
};
dma2: dma@40026400 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40026400 0x400>;
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
}; };
otghs_fs_phy: otghs_fs_phy { otghs_fs_phy: otghs_fs_phy {

11
dts/arm/st/l0/stm32l0.dtsi
View file

@ -180,6 +180,17 @@
label = "ADC_1"; label = "ADC_1";
#io-channel-cells = <1>; #io-channel-cells = <1>;
}; };
dma1: dma@40020000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020000 0x400>;
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
st,mem2mem;
status = "disabled";
label = "DMA_1";
};
}; };
}; };

22
dts/arm/st/l4/stm32l4.dtsi
View file

@ -310,6 +310,28 @@
label = "ADC_1"; label = "ADC_1";
#io-channel-cells = <1>; #io-channel-cells = <1>;
}; };
dma1: dma@40020000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020000 0x400>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
st,mem2mem;
status = "disabled";
label = "DMA_1";
};
dma2: dma@40020400 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020400 0x400>;
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
}; };
}; };