From ff3889a0514695f2857ee9df3a16a1d683f208ae Mon Sep 17 00:00:00 2001 From: Song Qiang Date: Thu, 24 Oct 2019 12:34:28 +0800 Subject: [PATCH] dt-bindings: arm: st: add dts support for DMA of some series of stm32 Add dts support for f0/f1/f2/f3/f4/f7/l0/l4 series STM32. Signed-off-by: Song Qiang --- dts/arm/st/f0/stm32f0.dtsi | 11 +++++++++++ dts/arm/st/f0/stm32f072.dtsi | 4 ++++ dts/arm/st/f0/stm32f091.dtsi | 16 ++++++++++++++++ dts/arm/st/f1/stm32f1.dtsi | 11 +++++++++++ dts/arm/st/f1/stm32f103Xe.dtsi | 11 +++++++++++ dts/arm/st/f1/stm32f107.dtsi | 10 ++++++++++ dts/arm/st/f2/stm32f2.dtsi | 21 +++++++++++++++++++++ dts/arm/st/f3/stm32f3.dtsi | 11 +++++++++++ dts/arm/st/f3/stm32f303Xc.dtsi | 10 ++++++++++ dts/arm/st/f3/stm32f373Xc.dtsi | 10 ++++++++++ dts/arm/st/f4/stm32f4.dtsi | 21 +++++++++++++++++++++ dts/arm/st/f7/stm32f7.dtsi | 21 +++++++++++++++++++++ dts/arm/st/l0/stm32l0.dtsi | 11 +++++++++++ dts/arm/st/l4/stm32l4.dtsi | 22 ++++++++++++++++++++++ 14 files changed, 190 insertions(+) diff --git a/dts/arm/st/f0/stm32f0.dtsi b/dts/arm/st/f0/stm32f0.dtsi index 5acf9225d95..1e7032c0ca7 100644 --- a/dts/arm/st/f0/stm32f0.dtsi +++ b/dts/arm/st/f0/stm32f0.dtsi @@ -311,6 +311,17 @@ label = "ADC_1"; #io-channel-cells = <1>; }; + + dma1: dma@40020000 { + compatible = "st,stm32-dma"; + #dma-cells = <4>; + reg = <0x40020000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>; + interrupts = <9 0 10 0 10 0 11 0 11 0>; + st,mem2mem; + status = "disabled"; + label = "DMA_1"; + }; }; }; diff --git a/dts/arm/st/f0/stm32f072.dtsi b/dts/arm/st/f0/stm32f072.dtsi index 0f859fe53c8..f73ff78a68d 100644 --- a/dts/arm/st/f0/stm32f072.dtsi +++ b/dts/arm/st/f0/stm32f072.dtsi @@ -81,6 +81,10 @@ phase-seg1 = <5>; phase-seg2 = <6>; }; + + dma1: dma@40020000 { + interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>; + }; }; usb_fs_phy: usbphy { diff --git a/dts/arm/st/f0/stm32f091.dtsi b/dts/arm/st/f0/stm32f091.dtsi index eb0c7db401b..ed96dc9338c 100644 --- a/dts/arm/st/f0/stm32f091.dtsi +++ b/dts/arm/st/f0/stm32f091.dtsi @@ -52,5 +52,21 @@ label = "GPIOE"; }; }; + + dma1: dma@40020000 { + interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>; + }; + + dma2: dma@40020400 { + compatible = "st,stm32-dma"; + #dma-cells = <4>; + reg = <0x40020400 0x400>; + interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 + 11 0 10 0 10 0 11 0 11 0 11 0>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>; + st,mem2mem; + status = "disabled"; + label = "DMA_2"; + }; }; }; diff --git a/dts/arm/st/f1/stm32f1.dtsi b/dts/arm/st/f1/stm32f1.dtsi index ca5dde36af5..0146e3d43b2 100644 --- a/dts/arm/st/f1/stm32f1.dtsi +++ b/dts/arm/st/f1/stm32f1.dtsi @@ -245,6 +245,17 @@ label = "ADC_1"; #io-channel-cells = <1>; }; + + dma1: dma@40020000 { + compatible = "st,stm32-dma"; + #dma-cells = <4>; + reg = <0x40020000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>; + interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; + st,mem2mem; + status = "disabled"; + label = "DMA_1"; + }; }; }; diff --git a/dts/arm/st/f1/stm32f103Xe.dtsi b/dts/arm/st/f1/stm32f103Xe.dtsi index 4f9f316025b..406de2350b6 100644 --- a/dts/arm/st/f1/stm32f103Xe.dtsi +++ b/dts/arm/st/f1/stm32f103Xe.dtsi @@ -134,5 +134,16 @@ #pwm-cells = <2>; }; }; + + dma2: dma@40020400 { + compatible = "st,stm32-dma"; + #dma-cells = <4>; + reg = <0x40020400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>; + interrupts = < 56 0 57 0 58 0 59 0 60 0>; + st,mem2mem; + status = "disabled"; + label = "DMA_1"; + }; }; }; diff --git a/dts/arm/st/f1/stm32f107.dtsi b/dts/arm/st/f1/stm32f107.dtsi index 319bcb10e38..5734bc0dc0b 100644 --- a/dts/arm/st/f1/stm32f107.dtsi +++ b/dts/arm/st/f1/stm32f107.dtsi @@ -73,5 +73,15 @@ #pwm-cells = <2>; }; }; + + dma2: dma@40020400 { + compatible = "st,stm32-dma"; + reg = <0x40020400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>; + interrupts = <56 0 57 0 58 0 59 0 60 0>; + st,mem2mem; + status = "disabled"; + label = "DMA_2"; + }; }; }; diff --git a/dts/arm/st/f2/stm32f2.dtsi b/dts/arm/st/f2/stm32f2.dtsi index bdf8bd85f2b..218d62d09db 100644 --- a/dts/arm/st/f2/stm32f2.dtsi +++ b/dts/arm/st/f2/stm32f2.dtsi @@ -232,6 +232,27 @@ label = "ADC_1"; #io-channel-cells = <1>; }; + + dma1: dma@40026000 { + compatible = "st,stm32-dma"; + #dma-cells = <4>; + reg = <0x40026000 0x400>; + interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>; + status = "disabled"; + label = "DMA_1"; + }; + + dma2: dma@40026400 { + compatible = "st,stm32-dma"; + #dma-cells = <4>; + reg = <0x40026400 0x400>; + interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>; + st,mem2mem; + status = "disabled"; + label = "DMA_2"; + }; }; otgfs_phy: otgfs_phy { diff --git a/dts/arm/st/f3/stm32f3.dtsi b/dts/arm/st/f3/stm32f3.dtsi index 995cabad20c..ddc057bb0a0 100644 --- a/dts/arm/st/f3/stm32f3.dtsi +++ b/dts/arm/st/f3/stm32f3.dtsi @@ -316,6 +316,17 @@ label = "ADC_1"; #io-channel-cells = <1>; }; + + dma1: dma@40020000 { + compatible = "st,stm32-dma"; + #dma-cells = <4>; + reg = <0x40020000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>; + interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; + st,mem2mem; + status = "disabled"; + label = "DMA_1"; + }; }; usb_fs_phy: usbphy { diff --git a/dts/arm/st/f3/stm32f303Xc.dtsi b/dts/arm/st/f3/stm32f303Xc.dtsi index e520df3b6a7..7e39799bacd 100644 --- a/dts/arm/st/f3/stm32f303Xc.dtsi +++ b/dts/arm/st/f3/stm32f303Xc.dtsi @@ -23,5 +23,15 @@ reg = <0x08000000 DT_SIZE_K(256)>; }; }; + + dma2: dma@40020400 { + compatible = "st,stm32-dma"; + #dma-cells = <4>; + reg = <0x40020400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>; + interrupts = <56 0 57 0 58 0 59 0 60 0>; + status = "disabled"; + label = "DMA_2"; + }; }; }; diff --git a/dts/arm/st/f3/stm32f373Xc.dtsi b/dts/arm/st/f3/stm32f373Xc.dtsi index 7a875091b53..d45b10a5ff8 100644 --- a/dts/arm/st/f3/stm32f373Xc.dtsi +++ b/dts/arm/st/f3/stm32f373Xc.dtsi @@ -18,5 +18,15 @@ reg = <0x08000000 DT_SIZE_K(256)>; }; }; + + dma2: dma@40020400 { + compatible = "st,stm32-dma"; + reg = <0x40020400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>; + interrupts = <56 0 57 0 58 0 59 0 60 0>; + st,mem2mem; + status = "disabled"; + label = "DMA_2"; + }; }; }; diff --git a/dts/arm/st/f4/stm32f4.dtsi b/dts/arm/st/f4/stm32f4.dtsi index 75993e06c1e..8ccfe34bc10 100644 --- a/dts/arm/st/f4/stm32f4.dtsi +++ b/dts/arm/st/f4/stm32f4.dtsi @@ -378,6 +378,27 @@ label = "ADC_1"; #io-channel-cells = <1>; }; + + dma1: dma@40026000 { + compatible = "st,stm32-dma"; + #dma-cells = <4>; + reg = <0x40026000 0x400>; + interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>; + status = "disabled"; + label = "DMA_1"; + }; + + dma2: dma@40026400 { + compatible = "st,stm32-dma"; + #dma-cells = <4>; + reg = <0x40026400 0x400>; + interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>; + st,mem2mem; + status = "disabled"; + label = "DMA_2"; + }; }; otgfs_phy: otgfs_phy { diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi index 835cedfb80f..0a96eb94309 100644 --- a/dts/arm/st/f7/stm32f7.dtsi +++ b/dts/arm/st/f7/stm32f7.dtsi @@ -619,6 +619,27 @@ label = "ADC_1"; #io-channel-cells = <1>; }; + + dma1: dma@40026000 { + compatible = "st,stm32-dma"; + #dma-cells = <4>; + reg = <0x40026000 0x400>; + interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>; + status = "disabled"; + label = "DMA_1"; + }; + + dma2: dma@40026400 { + compatible = "st,stm32-dma"; + #dma-cells = <4>; + reg = <0x40026400 0x400>; + interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>; + st,mem2mem; + status = "disabled"; + label = "DMA_2"; + }; }; otghs_fs_phy: otghs_fs_phy { diff --git a/dts/arm/st/l0/stm32l0.dtsi b/dts/arm/st/l0/stm32l0.dtsi index 58913707a5d..2f2e5decf45 100644 --- a/dts/arm/st/l0/stm32l0.dtsi +++ b/dts/arm/st/l0/stm32l0.dtsi @@ -180,6 +180,17 @@ label = "ADC_1"; #io-channel-cells = <1>; }; + + dma1: dma@40020000 { + compatible = "st,stm32-dma"; + #dma-cells = <4>; + reg = <0x40020000 0x400>; + interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>; + st,mem2mem; + status = "disabled"; + label = "DMA_1"; + }; }; }; diff --git a/dts/arm/st/l4/stm32l4.dtsi b/dts/arm/st/l4/stm32l4.dtsi index 88443e7fc39..58d2c422efc 100644 --- a/dts/arm/st/l4/stm32l4.dtsi +++ b/dts/arm/st/l4/stm32l4.dtsi @@ -310,6 +310,28 @@ label = "ADC_1"; #io-channel-cells = <1>; }; + + dma1: dma@40020000 { + compatible = "st,stm32-dma"; + #dma-cells = <4>; + reg = <0x40020000 0x400>; + interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>; + st,mem2mem; + status = "disabled"; + label = "DMA_1"; + }; + + dma2: dma@40020400 { + compatible = "st,stm32-dma"; + #dma-cells = <4>; + reg = <0x40020400 0x400>; + interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>; + st,mem2mem; + status = "disabled"; + label = "DMA_2"; + }; }; };