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x86: intel64: set the WP bit for paging

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Otherwise, supervisor mode can write to read-only areas,
failing tests that check this.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2019-10-10 16:31:13 -07:00 • committed by Andrew Boie
commit fdd3ba896a
1 changed files with 1 additions and 1 deletions
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arch/x86/core/intel64/locore.S
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@ -118,7 +118,7 @@ go64: movl %cr4, %eax /* enable PAE and SSE */
wrmsr
movl %cr0, %eax /* enable paging */
orl $CR0_PG, %eax
orl $(CR0_PG | CR0_WP), %eax
movl %eax, %cr0
jmpl $X86_KERNEL_CS, $1f