michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup

Browse source 
Convert the ns16550 driver to use the new centralized runtime BDF lookup
of PCIe devices.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
This commit is contained in:
Johan Hedberg 2022-11-09 13:21:47 +02:00 • committed by Carles Cufí
commit fcfff0633e
4 changed files with 68 additions and 57 deletions
Download patch file Download diff file Expand all files Collapse all files

29
drivers/serial/uart_ns16550.c
View file

@ -237,9 +237,7 @@ struct uart_ns16550_device_config {
#endif #endif
uint8_t reg_interval; uint8_t reg_interval;
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
bool pcie; struct pcie_dev *pcie;
pcie_bdf_t pcie_bdf;
pcie_id_t pcie_id;
#endif #endif
}; };
@ -335,13 +333,13 @@ static int uart_ns16550_configure(const struct device *dev,
if (dev_cfg->pcie) { if (dev_cfg->pcie) {
struct pcie_bar mbar; struct pcie_bar mbar;
if (!pcie_probe(dev_cfg->pcie_bdf, dev_cfg->pcie_id)) { if (dev_cfg->pcie->bdf == PCIE_BDF_NONE) {
ret = -EINVAL; ret = -EINVAL;
goto out; goto out;
} }
pcie_probe_mbar(dev_cfg->pcie_bdf, 0, &mbar); pcie_probe_mbar(dev_cfg->pcie->bdf, 0, &mbar);
pcie_set_cmd(dev_cfg->pcie_bdf, PCIE_CONF_CMDSTAT_MEM, true); pcie_set_cmd(dev_cfg->pcie->bdf, PCIE_CONF_CMDSTAT_MEM, true);
device_map(DEVICE_MMIO_RAM_PTR(dev), mbar.phys_addr, mbar.size, device_map(DEVICE_MMIO_RAM_PTR(dev), mbar.phys_addr, mbar.size,
K_MEM_CACHE_NONE); K_MEM_CACHE_NONE);
@ -1061,21 +1059,21 @@ static const struct uart_driver_api uart_ns16550_driver_api = {
#define UART_NS16550_IRQ_CONFIG_PCIE1(n) \ #define UART_NS16550_IRQ_CONFIG_PCIE1(n) \
static void irq_config_func##n(const struct device *dev) \ static void irq_config_func##n(const struct device *dev) \
{ \ { \
ARG_UNUSED(dev); \
BUILD_ASSERT(DT_INST_IRQN(n) == PCIE_IRQ_DETECT, \ BUILD_ASSERT(DT_INST_IRQN(n) == PCIE_IRQ_DETECT, \
"Only runtime IRQ configuration is supported"); \ "Only runtime IRQ configuration is supported"); \
BUILD_ASSERT(IS_ENABLED(CONFIG_DYNAMIC_INTERRUPTS), \ BUILD_ASSERT(IS_ENABLED(CONFIG_DYNAMIC_INTERRUPTS), \
"NS16550 PCIe requires dynamic interrupts"); \ "NS16550 PCIe requires dynamic interrupts"); \
unsigned int irq = pcie_alloc_irq(DT_INST_REG_ADDR(n)); \ const struct uart_ns16550_device_config *dev_cfg = dev->config;\
unsigned int irq = pcie_alloc_irq(dev_cfg->pcie->bdf); \
if (irq == PCIE_CONF_INTR_IRQ_NONE) { \ if (irq == PCIE_CONF_INTR_IRQ_NONE) { \
return; \ return; \
} \ } \
pcie_connect_dynamic_irq(DT_INST_REG_ADDR(n), irq, \ pcie_connect_dynamic_irq(dev_cfg->pcie->bdf, irq, \
DT_INST_IRQ(n, priority), \ DT_INST_IRQ(n, priority), \
(void (*)(const void *))uart_ns16550_isr, \ (void (*)(const void *))uart_ns16550_isr, \
DEVICE_DT_INST_GET(n), \ DEVICE_DT_INST_GET(n), \
UART_NS16550_IRQ_FLAGS(n)); \ UART_NS16550_IRQ_FLAGS(n)); \
pcie_irq_enable(DT_INST_REG_ADDR(n), irq); \ pcie_irq_enable(dev_cfg->pcie->bdf, irq); \
} }
#ifdef CONFIG_UART_NS16550_ACCESS_IOPORT #ifdef CONFIG_UART_NS16550_ACCESS_IOPORT
@ -1109,13 +1107,15 @@ static const struct uart_driver_api uart_ns16550_driver_api = {
#endif #endif
#define DEV_CONFIG_PCIE0(n) #define DEV_CONFIG_PCIE0(n)
#define DEV_CONFIG_PCIE1(n) \ #define DEV_CONFIG_PCIE1(n) DEVICE_PCIE_INST_INIT(n, pcie)
.pcie = true, \
.pcie_bdf = DT_INST_REG_ADDR(n), \
.pcie_id = DT_INST_REG_SIZE(n),
#define DEV_CONFIG_PCIE_INIT(n) \ #define DEV_CONFIG_PCIE_INIT(n) \
_CONCAT(DEV_CONFIG_PCIE, DT_INST_ON_BUS(n, pcie))(n) _CONCAT(DEV_CONFIG_PCIE, DT_INST_ON_BUS(n, pcie))(n)
#define DEV_DECLARE_PCIE0(n)
#define DEV_DECLARE_PCIE1(n) DEVICE_PCIE_INST_DECLARE(n)
#define DEV_PCIE_DECLARE(n) \
_CONCAT(DEV_DECLARE_PCIE, DT_INST_ON_BUS(n, pcie))(n)
#define DEV_DATA_FLOW_CTRL0 UART_CFG_FLOW_CTRL_NONE #define DEV_DATA_FLOW_CTRL0 UART_CFG_FLOW_CTRL_NONE
#define DEV_DATA_FLOW_CTRL1 UART_CFG_FLOW_CTRL_RTS_CTS #define DEV_DATA_FLOW_CTRL1 UART_CFG_FLOW_CTRL_RTS_CTS
#define DEV_DATA_FLOW_CTRL(n) \ #define DEV_DATA_FLOW_CTRL(n) \
@ -1129,6 +1129,7 @@ static const struct uart_driver_api uart_ns16550_driver_api = {
#define UART_NS16550_DEVICE_INIT(n) \ #define UART_NS16550_DEVICE_INIT(n) \
UART_NS16550_IRQ_FUNC_DECLARE(n); \ UART_NS16550_IRQ_FUNC_DECLARE(n); \
DEV_PCIE_DECLARE(n); \
static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_##n = { \ static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_##n = { \
DEV_CONFIG_REG_INIT(n) \ DEV_CONFIG_REG_INIT(n) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(n, clock_frequency), ( \ COND_CODE_1(DT_INST_NODE_HAS_PROP(n, clock_frequency), ( \

5
dts/bindings/serial/ns16550.yaml
View file

@ -2,12 +2,9 @@ description: ns16550 UART
compatible: "ns16550" compatible: "ns16550"
include: uart-controller.yaml include: [uart-controller.yaml, pcie-device.yaml]
properties: properties:
reg:
required: true
reg-shift: reg-shift:
type: int type: int
required: true required: true

28
dts/x86/intel/apollo_lake.dtsi
View file

@ -41,12 +41,13 @@
compatible = "intel,pcie"; compatible = "intel,pcie";
ranges; ranges;
uart0: uart@c000 { uart0: uart0 {
compatible = "ns16550"; compatible = "ns16550";
reg = <PCIE_BDF(0,0x18,0) PCIE_ID(0x8086,0x5abc)>; vendor-id = <0x8086>;
reg-shift = <2>; device-id = <0x5abc>;
reg-shift = <2>;
clock-frequency = <1843200>; clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
@ -54,12 +55,13 @@
current-speed = <115200>; current-speed = <115200>;
}; };
uart1: uart@c100 { uart1: uart1 {
compatible = "ns16550"; compatible = "ns16550";
reg = <PCIE_BDF(0,0x18,1) PCIE_ID(0x8086,0x5abe)>; vendor-id = <0x8086>;
reg-shift = <2>; device-id = <0x5abe>;
reg-shift = <2>;
clock-frequency = <1843200>; clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
@ -68,12 +70,13 @@
current-speed = <115200>; current-speed = <115200>;
}; };
uart2: uart@c200 { uart2: uart2 {
compatible = "ns16550"; compatible = "ns16550";
reg = <PCIE_BDF(0,0x18,2) PCIE_ID(0x8086,0x5ac0)>; vendor-id = <0x8086>;
reg-shift = <2>; device-id = <0x5ac0>;
reg-shift = <2>;
clock-frequency = <1843200>; clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
@ -82,12 +85,13 @@
current-speed = <115200>; current-speed = <115200>;
}; };
uart3: uart@c300 { uart3: uart3 {
compatible = "ns16550"; compatible = "ns16550";
reg = <PCIE_BDF(0,0x18,3) PCIE_ID(0x8086,0x5aee)>; vendor-id = <0x8086>;
reg-shift = <2>; device-id = <0x5aee>;
reg-shift = <2>;
clock-frequency = <1843200>; clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;

63
dts/x86/intel/elkhart_lake.dtsi
View file

@ -54,12 +54,13 @@
status = "okay"; status = "okay";
}; };
uart0: uart@f000 { uart0: uart0 {
compatible = "ns16550"; compatible = "ns16550";
reg = <PCIE_BDF(0,0x1e,0) PCIE_ID(0x8086,0x4b28)>; vendor-id = <0x8086>;
reg-shift = <2>; device-id = <0x4b28>;
reg-shift = <2>;
clock-frequency = <1843200>; clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
@ -67,12 +68,13 @@
current-speed = <115200>; current-speed = <115200>;
}; };
uart1: uart@f100 { uart1: uart1 {
compatible = "ns16550"; compatible = "ns16550";
reg = <PCIE_BDF(0,0x1e,1) PCIE_ID(0x8086,0x4b29)>; vendor-id = <0x8086>;
reg-shift = <2>; device-id = <0x4b29>;
reg-shift = <2>;
clock-frequency = <1843200>; clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
@ -81,12 +83,13 @@
current-speed = <115200>; current-speed = <115200>;
}; };
uart2: uart@ca00 { uart2: uart2 {
compatible = "ns16550"; compatible = "ns16550";
reg = <PCIE_BDF(0,0x19,2) PCIE_ID(0x8086,0x4b4d)>; vendor-id = <0x8086>;
reg-shift = <2>; device-id = <0x4b4d>;
reg-shift = <2>;
clock-frequency = <1843200>; clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
@ -95,12 +98,13 @@
current-speed = <115200>; current-speed = <115200>;
}; };
uart_pse_0: uart@8800 { uart_pse_0: uart_pse_0 {
compatible = "ns16550"; compatible = "ns16550";
reg = <PCIE_BDF(0,0x11,0) PCIE_ID(0x8086,0x4b96)>; vendor-id = <0x8086>;
reg-shift = <2>; device-id = <0x4b96>;
reg-shift = <2>;
clock-frequency = <1843200>; clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
@ -109,12 +113,13 @@
current-speed = <115200>; current-speed = <115200>;
}; };
uart_pse_1: uart@8900 { uart_pse_1: uart_pse_1 {
compatible = "ns16550"; compatible = "ns16550";
reg = <PCIE_BDF(0,0x11,1) PCIE_ID(0x8086,0x4b97)>; vendor-id = <0x8086>;
reg-shift = <2>; device-id = <0x4b97>;
reg-shift = <2>;
clock-frequency = <1843200>; clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
@ -123,12 +128,13 @@
current-speed = <115200>; current-speed = <115200>;
}; };
uart_pse_2: uart@8a00 { uart_pse_2: uart_pse_2 {
compatible = "ns16550"; compatible = "ns16550";
reg = <PCIE_BDF(0,0x11,2) PCIE_ID(0x8086,0x4b98)>; vendor-id = <0x8086>;
reg-shift = <2>; device-id = <0x4b98>;
reg-shift = <2>;
clock-frequency = <1843200>; clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
@ -137,12 +143,13 @@
current-speed = <115200>; current-speed = <115200>;
}; };
uart_pse_3: uart@8b00 { uart_pse_3: uart_pse_3 {
compatible = "ns16550"; compatible = "ns16550";
reg = <PCIE_BDF(0,0x11,3) PCIE_ID(0x8086,0x4b99)>; vendor-id = <0x8086>;
reg-shift = <2>; device-id = <0x4b99>;
reg-shift = <2>;
clock-frequency = <1843200>; clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
@ -151,12 +158,13 @@
current-speed = <115200>; current-speed = <115200>;
}; };
uart_pse_4: uart@8c00 { uart_pse_4: uart_pse_4 {
compatible = "ns16550"; compatible = "ns16550";
reg = <PCIE_BDF(0,0x11,4) PCIE_ID(0x8086,0x4b9a)>; vendor-id = <0x8086>;
reg-shift = <2>; device-id = <0x4b9a>;
reg-shift = <2>;
clock-frequency = <1843200>; clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
@ -165,12 +173,13 @@
current-speed = <115200>; current-speed = <115200>;
}; };
uart_pse_5: uart@8d00 { uart_pse_5: uart_pse_5 {
compatible = "ns16550"; compatible = "ns16550";
reg = <PCIE_BDF(0,0x11,5) PCIE_ID(0x8086,0x4b9b)>; vendor-id = <0x8086>;
reg-shift = <2>; device-id = <0x4b9b>;
reg-shift = <2>;
clock-frequency = <1843200>; clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;