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arm float: Save and load FP registers

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Saves and loads the non-volatile FP registers (s16-s31) when switching
between threads.

Change-Id: Ib3190452d9a70d722032ac83176eb4fbb92aca3d
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
This commit is contained in:
Peter Mitsis 2016-05-13 14:22:46 -04:00 • committed by Maureen Helm
commit fc8b2a2064
1 changed files with 10 additions and 0 deletions
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10
arch/arm/core/swap.S
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@ -76,6 +76,11 @@ SECTION_FUNC(TEXT, __pendsv)
mrs ip, PSP mrs ip, PSP
stmia r0, {v1-v8, ip} stmia r0, {v1-v8, ip}
#ifdef CONFIG_FP_SHARING
add r0, r2, #__tTCS_preemp_float_regs_OFFSET
vstmia r0, {s16-s31}
#endif
/* /*
* Prepare to clear PendSV with interrupts unlocked, but * Prepare to clear PendSV with interrupts unlocked, but
* don't clear it yet. PendSV must not be cleared until * don't clear it yet. PendSV must not be cleared until
@ -128,6 +133,11 @@ SECTION_FUNC(TEXT, __pendsv)
str ip, [r2, #__tTCS_basepri_OFFSET] str ip, [r2, #__tTCS_basepri_OFFSET]
msr BASEPRI, r0 msr BASEPRI, r0
#ifdef CONFIG_FP_SHARING
add r0, r2, #__tTCS_preemp_float_regs_OFFSET
vldmia r0, {s16-s31}
#endif
/* load callee-saved + psp from TCS */ /* load callee-saved + psp from TCS */
add r0, r2, #__tTCS_preempReg_OFFSET add r0, r2, #__tTCS_preempReg_OFFSET
ldmia r0, {v1-v8, ip} ldmia r0, {v1-v8, ip}