From fc8b2a2064c8f72207087ba50da8a8b7eb4961f7 Mon Sep 17 00:00:00 2001 From: Peter Mitsis Date: Fri, 13 May 2016 14:22:46 -0400 Subject: [PATCH] arm float: Save and load FP registers Saves and loads the non-volatile FP registers (s16-s31) when switching between threads. Change-Id: Ib3190452d9a70d722032ac83176eb4fbb92aca3d Signed-off-by: Peter Mitsis --- arch/arm/core/swap.S | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/core/swap.S b/arch/arm/core/swap.S index 7a2fc19e6a9..d2aaecbeda6 100644 --- a/arch/arm/core/swap.S +++ b/arch/arm/core/swap.S @@ -76,6 +76,11 @@ SECTION_FUNC(TEXT, __pendsv) mrs ip, PSP stmia r0, {v1-v8, ip} +#ifdef CONFIG_FP_SHARING + add r0, r2, #__tTCS_preemp_float_regs_OFFSET + vstmia r0, {s16-s31} +#endif + /* * Prepare to clear PendSV with interrupts unlocked, but * don't clear it yet. PendSV must not be cleared until @@ -128,6 +133,11 @@ SECTION_FUNC(TEXT, __pendsv) str ip, [r2, #__tTCS_basepri_OFFSET] msr BASEPRI, r0 +#ifdef CONFIG_FP_SHARING + add r0, r2, #__tTCS_preemp_float_regs_OFFSET + vldmia r0, {s16-s31} +#endif + /* load callee-saved + psp from TCS */ add r0, r2, #__tTCS_preempReg_OFFSET ldmia r0, {v1-v8, ip}