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soc: intel_s1000: define default MEMCTL reg value

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When not using XCC, XCHAL_CACHE_MEMCTL_DEFAULT is not defined
which results in some variables not being able to be defined.
So define them.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2019-08-29 12:13:00 -07:00 • committed by Kumar Gala
commit fc42c82cb9
1 changed files with 3 additions and 0 deletions
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3
soc/xtensa/intel_s1000/linker.ld
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@ -139,6 +139,9 @@ PHDRS
_rom_store_table = 0; _rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM); PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
PROVIDE(__memctl_default = 0xFFFFFF00);
PROVIDE(_MemErrorHandler = 0xFFFFFF00);
ENTRY(CONFIG_KERNEL_ENTRY) ENTRY(CONFIG_KERNEL_ENTRY)
/* Various memory-map dependent cache attribute settings: */ /* Various memory-map dependent cache attribute settings: */