From fc42c82cb9ab9cde82972c614e6b5294c9c6a8c3 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Thu, 29 Aug 2019 12:13:00 -0700 Subject: [PATCH] soc: intel_s1000: define default MEMCTL reg value When not using XCC, XCHAL_CACHE_MEMCTL_DEFAULT is not defined which results in some variables not being able to be defined. So define them. Signed-off-by: Daniel Leung --- soc/xtensa/intel_s1000/linker.ld | 3 +++ 1 file changed, 3 insertions(+) diff --git a/soc/xtensa/intel_s1000/linker.ld b/soc/xtensa/intel_s1000/linker.ld index 2055754f899..a2298c8d990 100644 --- a/soc/xtensa/intel_s1000/linker.ld +++ b/soc/xtensa/intel_s1000/linker.ld @@ -139,6 +139,9 @@ PHDRS _rom_store_table = 0; PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM); +PROVIDE(__memctl_default = 0xFFFFFF00); +PROVIDE(_MemErrorHandler = 0xFFFFFF00); + ENTRY(CONFIG_KERNEL_ENTRY) /* Various memory-map dependent cache attribute settings: */