dts: arm: Rename ARM NVIC compatibility
Reworking the ARM NVIC binding and cleaning it up. Towards this introduce a new compatibility for this new binding. So we rename arm,armv{6,7}-nvic to arm,v{6,7}-nvic (for new binding). We also just use the bit more generic arm,nvic in device tree files. Change-Id: I5a2c45313ed94619d9268f2c035dacbc8acded29 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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12 changed files with 43 additions and 11 deletions
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@ -9,7 +9,7 @@
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ranges;
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nvic: interrupt-controller@e000e100 {
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compatible = "arm,armv6m-nvic";
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compatible = "arm,nvic";
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reg = <0xe000e100 0xc00>;
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interrupt-controller;
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#interrupt-cells = <2>;
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@ -9,7 +9,7 @@
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ranges;
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nvic: interrupt-controller@e000e100 {
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compatible = "arm,armv7m-nvic";
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compatible = "arm,nvic";
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reg = <0xe000e100 0xc00>;
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interrupt-controller;
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#interrupt-cells = <2>;
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@ -1,4 +1,4 @@
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define EXCEPTION_UARTA0 TI_CC32XX_UART_4000C000_IRQ_0
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#define CONFIG_UART_CC32XX_IRQ_PRI TI_CC32XX_UART_4000C000_IRQ_0_PRIORITY
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE
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#define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_IRQ_0_PRIORITY
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV6M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CONFIG_UART_MCUX_LPUART_0_BAUD_RATE NXP_KW41Z_LPUART_40054000_BAUD_RATE
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#define CONFIG_UART_MCUX_LPUART_0_IRQ_PRI NXP_KW41Z_LPUART_40054000_IRQ_0_PRIORITY
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE
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#define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_IRQ_0_PRIORITY
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* generated data matches the driver definitions.
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*/
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS
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#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE
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*/
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS
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#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CMSDK_APB_UART_0_IRQ ARM_CMSDK_UART_40004000_IRQ_0
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#define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY
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32
dts/arm/yaml/arm,nvic.yaml
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32
dts/arm/yaml/arm,nvic.yaml
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---
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title: ARM Cortex-M NVIC Interrupt Controller
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version: 0.1
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description: >
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This binding describes the ARM Cortex-M NVIC IRQ controller
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properties:
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- compatible:
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category: required
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type: string
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description: compatible strings
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constraint: "arm,nvic"
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- reg:
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category: required
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type: int
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description: mmio register space
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generation: define
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- num-irq-prio-bits:
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category: required
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type: int
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description: number of bits of IRQ priorities
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generation: define
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cell_string: IRQ
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"#cells":
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- irq
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- priority
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...
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@ -10,7 +10,7 @@ properties:
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category: required
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type: string
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description: compatible strings
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constraint: "arm,armv6m-nvic"
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constraint: "arm,v6m-nvic"
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- reg:
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category: required
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@ -10,7 +10,7 @@ properties:
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category: required
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type: string
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description: compatible strings
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constraint: "arm,armv7m-nvic"
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constraint: "arm,v7m-nvic"
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- reg:
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category: required
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