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dts: arm: Rename ARM NVIC compatibility

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Reworking the ARM NVIC binding and cleaning it up.  Towards this
introduce a new compatibility for this new binding.  So we rename
arm,armv{6,7}-nvic to arm,v{6,7}-nvic (for new binding).  We also just
use the bit more generic arm,nvic in device tree files.

Change-Id: I5a2c45313ed94619d9268f2c035dacbc8acded29
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-03-27 11:57:52 -05:00
commit fbc55198e7
12 changed files with 43 additions and 11 deletions
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2
dts/arm/armv6-m.dtsi
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@ -9,7 +9,7 @@
ranges; ranges;
nvic: interrupt-controller@e000e100 { nvic: interrupt-controller@e000e100 {
compatible = "arm,armv6m-nvic"; compatible = "arm,nvic";
reg = <0xe000e100 0xc00>; reg = <0xe000e100 0xc00>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;

2
dts/arm/armv7-m.dtsi
View file

@ -9,7 +9,7 @@
ranges; ranges;
nvic: interrupt-controller@e000e100 { nvic: interrupt-controller@e000e100 {
compatible = "arm,armv7m-nvic"; compatible = "arm,nvic";
reg = <0xe000e100 0xc00>; reg = <0xe000e100 0xc00>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;

2
dts/arm/cc3200_launchxl.fixup
View file

@ -1,4 +1,4 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS #define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define EXCEPTION_UARTA0 TI_CC32XX_UART_4000C000_IRQ_0 #define EXCEPTION_UARTA0 TI_CC32XX_UART_4000C000_IRQ_0
#define CONFIG_UART_CC32XX_IRQ_PRI TI_CC32XX_UART_4000C000_IRQ_0_PRIORITY #define CONFIG_UART_CC32XX_IRQ_PRI TI_CC32XX_UART_4000C000_IRQ_0_PRIORITY

2
dts/arm/frdm_k64f.fixup
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@ -1,4 +1,4 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS #define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE #define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE
#define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_IRQ_0_PRIORITY #define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_IRQ_0_PRIORITY

2
dts/arm/frdm_kw41z.fixup
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@ -1,4 +1,4 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV6M_NVIC_E000E100_NUM_IRQ_PRIO_BITS #define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CONFIG_UART_MCUX_LPUART_0_BAUD_RATE NXP_KW41Z_LPUART_40054000_BAUD_RATE #define CONFIG_UART_MCUX_LPUART_0_BAUD_RATE NXP_KW41Z_LPUART_40054000_BAUD_RATE
#define CONFIG_UART_MCUX_LPUART_0_IRQ_PRI NXP_KW41Z_LPUART_40054000_IRQ_0_PRIORITY #define CONFIG_UART_MCUX_LPUART_0_IRQ_PRI NXP_KW41Z_LPUART_40054000_IRQ_0_PRIORITY

2
dts/arm/hexiwear_k64.fixup
View file

@ -1,4 +1,4 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS #define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE #define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE
#define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_IRQ_0_PRIORITY #define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_IRQ_0_PRIORITY

2
dts/arm/nucleo_l476rg.fixup
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@ -4,7 +4,7 @@
* generated data matches the driver definitions. * generated data matches the driver definitions.
*/ */
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS #define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS #define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE #define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE

2
dts/arm/olimexino_stm32.fixup
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@ -5,7 +5,7 @@
*/ */
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS #define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS #define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE #define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE

2
dts/arm/v2m_beetle.fixup
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@ -1,4 +1,4 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS #define CONFIG_NUM_IRQ_PRIO_BITS ARM_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CMSDK_APB_UART_0_IRQ ARM_CMSDK_UART_40004000_IRQ_0 #define CMSDK_APB_UART_0_IRQ ARM_CMSDK_UART_40004000_IRQ_0
#define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY #define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY

32
dts/arm/yaml/arm,nvic.yaml Normal file
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@ -0,0 +1,32 @@
---
title: ARM Cortex-M NVIC Interrupt Controller
version: 0.1
description: >
This binding describes the ARM Cortex-M NVIC IRQ controller
properties:
- compatible:
category: required
type: string
description: compatible strings
constraint: "arm,nvic"
- reg:
category: required
type: int
description: mmio register space
generation: define
- num-irq-prio-bits:
category: required
type: int
description: number of bits of IRQ priorities
generation: define
cell_string: IRQ
"#cells":
- irq
- priority
...

2
dts/arm/yaml/arm,armv6m-nvic.yaml → dts/arm/yaml/arm,v6m-nvic.yaml
View file

@ -10,7 +10,7 @@ properties:
category: required category: required
type: string type: string
description: compatible strings description: compatible strings
constraint: "arm,armv6m-nvic" constraint: "arm,v6m-nvic"
- reg: - reg:
category: required category: required

2
dts/arm/yaml/arm_cortex_m4_nvic.yaml → dts/arm/yaml/arm,v7m-nvic.yaml
View file

@ -10,7 +10,7 @@ properties:
category: required category: required
type: string type: string
description: compatible strings description: compatible strings
constraint: "arm,armv7m-nvic" constraint: "arm,v7m-nvic"
- reg: - reg:
category: required category: required