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soc: esp32c2: Add support to ESP32C2 and ESP8684

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Files for SoC support: ESP32C2 and ESP8684 (same core).
Basic device tree configuration.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
This commit is contained in:
Raffael Rostagno 2024-07-24 13:44:53 -03:00 • committed by Anas Nashif
commit fad55d18ad
25 changed files with 1971 additions and 6 deletions
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9
soc/espressif/common/Kconfig.defconfig
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@ -1,7 +1,7 @@
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
if SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
config GEN_ISR_TABLES
default y
@ -22,7 +22,8 @@ config ATOMIC_OPERATIONS_C
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 16000000
default 12000000 if SOC_SERIES_ESP32C2
default 16000000 if SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
config SYS_CLOCK_TICKS_PER_SEC
default 1000
@ -49,7 +50,7 @@ config ROM_START_OFFSET
endif # BOOTLOADER_MCUBOOT
endif # SOC_SERIES_ESP32C3
endif # SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3

4
soc/espressif/common/Kconfig.esptool
View file

@ -81,6 +81,7 @@ config ESPTOOLPY_FLASHMODE
choice ESPTOOLPY_FLASHFREQ
prompt "Flash SPI speed"
default ESPTOOLPY_FLASHFREQ_40M if SOC_SERIES_ESP32
default ESPTOOLPY_FLASHFREQ_60M if SOC_SERIES_ESP32C2
default ESPTOOLPY_FLASHFREQ_80M if ESPTOOLPY_FLASHFREQ_80M_DEFAULT
config ESPTOOLPY_FLASHFREQ_120M
@ -99,6 +100,8 @@ config ESPTOOLPY_FLASHFREQ_120M
config ESPTOOLPY_FLASHFREQ_80M
bool "80 MHz"
config ESPTOOLPY_FLASHFREQ_60M
bool "60 MHz"
config ESPTOOLPY_FLASHFREQ_40M
bool "40 MHz"
config ESPTOOLPY_FLASHFREQ_26M
@ -121,6 +124,7 @@ config ESPTOOLPY_FLASHFREQ
# We currently define this to `80m`.
default '80m' if ESPTOOLPY_FLASHFREQ_120M
default '80m' if ESPTOOLPY_FLASHFREQ_80M
default '60m' if ESPTOOLPY_FLASHFREQ_60M
default '40m' if ESPTOOLPY_FLASHFREQ_40M
default '26m' if ESPTOOLPY_FLASHFREQ_26M
default '20m' if ESPTOOLPY_FLASHFREQ_20M

2
soc/espressif/common/Kconfig.flash
View file

@ -94,7 +94,7 @@ config BOOTLOADER_FLASH_XMC_SUPPORT
choice BOOTLOADER_VDDSDIO_BOOST
bool "VDDSDIO LDO voltage"
default BOOTLOADER_VDDSDIO_BOOST_1_9V
depends on !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6
depends on !SOC_SERIES_ESP32C2 && !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6
help
If this option is enabled, and VDDSDIO LDO is set to 1.8V (using eFuse
or MTDI bootstrapping pin), bootloader will change LDO settings to

75
soc/espressif/esp32c2/CMakeLists.txt Normal file
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@ -0,0 +1,75 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(
vectors.S
soc_irq.S
soc_irq.c
soc.c
../common/loader.c
)
zephyr_include_directories(.)
# get flash size to use in esptool as string
math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
if(NOT CONFIG_BOOTLOADER_MCUBOOT)
if(CONFIG_BUILD_OUTPUT_BIN)
# make ESP ROM loader compatible image
message("ESP-IDF path: ${ESP_IDF_PATH}")
set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py)
message("esptool path: ${ESPTOOL_PY}")
set(ELF2IMAGE_ARG "")
if(NOT CONFIG_MCUBOOT)
set(ELF2IMAGE_ARG "--ram-only-header")
endif()
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY}
ARGS --chip esp32c2 elf2image ${ELF2IMAGE_ARG}
--flash_mode dio --flash_freq 60m --flash_size ${esptoolpy_flashsize}MB
-o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
endif()
endif()
# get code-partition slot0 address
dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
dt_reg_addr(img_0_off PATH ${dts_partition_path})
# get code-partition boot address
dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
dt_reg_addr(boot_off PATH ${dts_partition_path})
# C2 uses specific values for flash frequency and UART baudrate
board_runner_args(esp32 "--esp-flash-freq=60m")
board_runner_args(esp32 "--esp-monitor-baud=74880")
if(CONFIG_ESP_SIMPLE_BOOT)
board_finalize_runner_args(esp32 "--esp-app-address=${boot_off}")
else()
board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
endif()
if(CONFIG_MCUBOOT)
# search from cross references between bootloader sections
message("check_callgraph using: ${ESP_IDF_PATH}/tools/ci/check_callgraph.py")
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
COMMAND
${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/ci/check_callgraph.py
ARGS
--rtl-dirs ${CMAKE_BINARY_DIR}/zephyr
--elf-file ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf
find-refs --from-section=.iram0.iram_loader --to-section=.iram0.text
--exit-code)
endif()
if(CONFIG_MCUBOOT)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
else()
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
endif()

28
soc/espressif/esp32c2/Kconfig Normal file
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@ -0,0 +1,28 @@
# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_ESP32C2
select RISCV
select RISCV_GP
select DYNAMIC_INTERRUPTS
select CLOCK_CONTROL
select PINCTRL
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select HAS_ESPRESSIF_HAL
select XIP if !MCUBOOT
if SOC_SERIES_ESP32C2
config MAC_BB_PD
bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled"
depends on SOC_SERIES_ESP32C2 && TICKLESS_KERNEL
help
If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered
down when PHY is disabled. Enabling this setting reduces power consumption
by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only),
2 KB(Bluetooth only) or 5.3 KB(Wi-Fi + Bluetooth).
endif # SOC_SERIES_ESP32C2

17
soc/espressif/esp32c2/Kconfig.defconfig Normal file
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@ -0,0 +1,17 @@
# ESP32C2 SoC configuration
# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_ESP32C2
config NUM_IRQS
default 43
config FLASH_SIZE
default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0)
config FLASH_BASE_ADDRESS
default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0)
endif # SOC_SERIES_ESP32C2

48
soc/espressif/esp32c2/Kconfig.mac Normal file
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@ -0,0 +1,48 @@
# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_ESP32C2
choice ESP32C2_UNIVERSAL_MAC_ADDRESSES
bool "Number of universally administered (by IEEE) MAC address"
default ESP32C2_UNIVERSAL_MAC_ADDRESSES_FOUR
help
Configure the number of universally administered (by IEEE) MAC addresses.
During initialization, MAC addresses for each network interface are generated or derived from a
single base MAC address.
If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,
Bluetooth and Ethernet) receive a universally administered MAC address. These are generated
sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)
receive a universally administered MAC address. These are generated sequentially by adding 0
and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)
receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC
addresses, respectively.
When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
a custom universal MAC address range, the correct setting will depend on the allocation of MAC
addresses in this range (either 2 or 4 per device.)
Note that ESP32-C6 has no integrated Ethernet MAC. Although it's possible to use the esp_read_mac()
API to return a MAC for Ethernet, this can only be used with an external MAC peripheral.
config ESP32C2_UNIVERSAL_MAC_ADDRESSES_TWO
bool "Two"
select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_BT
config ESP32C2_UNIVERSAL_MAC_ADDRESSES_FOUR
bool "Four"
select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR
select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
select ESP_MAC_ADDR_UNIVERSE_BT
select ESP_MAC_ADDR_UNIVERSE_ETH
endchoice # ESP32C2_UNIVERSAL_MAC_ADDRESSES
config ESP32C2_UNIVERSAL_MAC_ADDRESSES
int
default 2 if ESP32C2_UNIVERSAL_MAC_ADDRESSES_TWO
default 4 if ESP32C2_UNIVERSAL_MAC_ADDRESSES_FOUR
endif # SOC_SERIES_ESP32C2

38
soc/espressif/esp32c2/Kconfig.soc Normal file
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@ -0,0 +1,38 @@
# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_ESP32C2
bool
select SOC_FAMILY_ESPRESSIF_ESP32
config SOC_ESP8684_MINI_H2
bool
select SOC_ESP32C2
config SOC_ESP8684_MINI_H4
bool
select SOC_ESP32C2
config SOC_ESP8684_WROOM_H2
bool
select SOC_ESP32C2
config SOC_ESP8684_WROOM_H4
bool
select SOC_ESP32C2
config SOC_ESP32C2
bool
select SOC_SERIES_ESP32C2
config SOC_SERIES
default "esp32c2" if SOC_SERIES_ESP32C2
config SOC
default "esp32c2" if SOC_ESP32C2
config SOC_PART_NUMBER
default "ESP8684_MINI_1_H2" if SOC_ESP8684_MINI_H2
default "ESP8684_MINI_1_H4" if SOC_ESP8684_MINI_H4
default "ESP8684_WROOM_01C_H2" if SOC_ESP8684_WROOM_H2
default "ESP8684_WROOM_01C_H4" if SOC_ESP8684_WROOM_H4

756
soc/espressif/esp32c2/default.ld Normal file
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@ -0,0 +1,756 @@
/*
* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/linker/sections.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/linker/linker-tool.h>
#include "memory.h"
/* The "user_iram_end" represents the 2nd stage bootloader
* "iram_loader_seg" start address (that should not be overlapped).
* If no bootloader is used, we can extend it to gain more user ram.
*/
#ifdef CONFIG_ESP_SIMPLE_BOOT
user_iram_end = (DRAM_BUFFERS_START + IRAM_DRAM_OFFSET);
#else
user_iram_end = BOOTLOADER_IRAM_LOADER_SEG_START;
#endif
/* User available SRAM memory segments */
user_iram_seg_org = SRAM1_IRAM_START;
user_dram_seg_org = SRAM1_DRAM_START;
user_dram_end = (user_iram_end - IRAM_DRAM_OFFSET);
user_idram_size = (user_dram_end - user_dram_seg_org);
user_iram_seg_len = user_idram_size;
user_dram_seg_len = user_idram_size;
/* Aliases */
#define FLASH_CODE_REGION irom0_0_seg
#define RODATA_REGION drom0_0_seg
#define IRAM_REGION iram0_0_seg
#define DRAM_REGION dram0_0_seg
#define RAMABLE_REGION dram0_0_seg
#define ROMABLE_REGION FLASH
/* Flash segments (rodata and text) should be mapped in the virtual address spaces.
* Executing directly from LMA is not possible. */
#undef GROUP_ROM_LINK_IN
#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion
/* Make sure new sections have consistent alignment between input and output sections */
#undef SECTION_PROLOGUE
#define SECTION_PROLOGUE SECTION_DATA_PROLOGUE
/* Global symbols required for espressif hal build */
MEMORY
{
#ifdef CONFIG_BOOTLOADER_MCUBOOT
mcuboot_hdr (R): org = 0x0, len = 0x20
metadata (R): org = 0x20, len = 0x20
FLASH (R): org = 0x40, len = FLASH_SIZE - 0x40
#else
/* Make safety margin in the FLASH memory size so the
* (esp_img_header + (n*esp_seg_headers)) would fit */
FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100
#endif
iram0_0_seg(RX): org = user_iram_seg_org, len = user_iram_seg_len
dram0_0_seg(RW): org = user_dram_seg_org, len = user_dram_seg_len
irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
drom0_0_seg (R): org = DROM_SEG_ORG, len = DROM_SEG_LEN
#ifdef CONFIG_GEN_ISR_TABLES
IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
#endif
}
/* Default entry point: */
ENTRY(CONFIG_KERNEL_ENTRY)
_rom_store_table = 0;
_iram_dram_offset = IRAM_DRAM_OFFSET;
SECTIONS
{
#ifdef CONFIG_BOOTLOADER_MCUBOOT
/* Reserve space for MCUboot header in the binary */
.mcuboot_header :
{
QUAD(0x0)
QUAD(0x0)
QUAD(0x0)
QUAD(0x0)
} > mcuboot_hdr
.metadata :
{
/* 0. Magic byte for load header */
LONG(0xace637d3)
/* 1. Application entry point address */
KEEP(*(.entry_addr))
/* IRAM metadata:
* 2. Destination address (VMA) for IRAM region
* 3. Flash offset (LMA) for start of IRAM region
* 4. Size of IRAM region
*/
LONG(ADDR(.iram0.text))
LONG(LOADADDR(.iram0.text))
LONG(LOADADDR(.iram0.data) - LOADADDR(.iram0.text))
/* DRAM metadata:
* 5. Destination address (VMA) for DRAM region
* 6. Flash offset (LMA) for start of DRAM region
* 7. Size of DRAM region
*/
LONG(ADDR(.dram0.data))
LONG(LOADADDR(.dram0.data))
LONG(LOADADDR(.dram0.end) - LOADADDR(.dram0.data))
} > metadata
#endif /* CONFIG_BOOTLOADER_MCUBOOT */
iram_vma = ADDR(.iram0.text);
iram_lma = LOADADDR(.iram0.text);
iram_size_field = LOADADDR(.iram0.data) - LOADADDR(.iram0.text);
dram_vma = ADDR(.dram0.data);
dram_lma = LOADADDR(.dram0.data);
dram_size_field = LOADADDR(.dram0.end) - LOADADDR(.dram0.data);
#include <zephyr/linker/rel-sections.ld>
#ifdef CONFIG_LLEXT
#include <zephyr/linker/llext-sections.ld>
#endif
/* --- START OF IRAM --- */
.iram0.text : ALIGN(4)
{
/* Vectors go to IRAM */
_iram_start = ABSOLUTE(.);
_init_start = ABSOLUTE(.);
KEEP(*(.exception_vectors.text));
. = ALIGN(256);
_invalid_pc_placeholder = ABSOLUTE(.);
KEEP(*(.exception.entry*)); /* contains _isr_wrapper */
*(.exception.other*)
. = ALIGN(4);
*(.entry.text)
*(.init.literal)
*(.init)
. = ALIGN(4);
_init_end = ABSOLUTE(.);
_iram_text_start = ABSOLUTE(.);
*(.iram1 .iram1.*)
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
*libzephyr.a:panic.*(.literal .text .literal.* .text.*)
*libzephyr.a:loader.*(.literal .text .literal.* .text.*)
*libarch__riscv__core.a:(.literal .text .literal.* .text.*)
*libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)
*libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)
*libsubsys__net__ip.a:(.literal .text .literal.* .text.*)
*libsubsys__net.a:(.literal .text .literal.* .text.*)
*libkernel.a:(.literal .text .literal.* .text.*)
*libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)
*libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)
*libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)
*libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)
*libdrivers__timer.a:esp32c2_sys_timer.*(.literal .text .literal.* .text.*)
*libzephyr.a:log_core.*(.literal .text .literal.* .text.*)
*libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)
*libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)
*libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)
*libzephyr.a:log_list.*(.literal .text .literal.* .text.*)
*libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)
*libzephyr.a:log_output.*(.literal .text .literal.* .text.*)
*libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)
*libzephyr.a:rtc_*.*(.literal .text .literal.* .text.*)
*liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*)
*liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)
*liblib__libc__picolib.a:string.*(.literal .text .literal.* .text.*)
*libzephyr.a:periph_ctrl.*(.literal .text .literal.* .text.*)
*libgcov.a:(.literal .text .literal.* .text.*)
*libphy.a:( .phyiram .phyiram.*)
*libc.a:*(.literal .text .literal.* .text.*)
/* [mapping:hal] */
*libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
*libzephyr.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*)
*libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .text .literal.* .text.*)
*libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*)
*libzephyr.a:ledc_hal_iram.*(.literal .text .literal.* .text.*)
*libzephyr.a:i2c_hal_iram.*(.literal .text .literal.* .text.*)
*libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*)
*libzephyr.a:spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*)
/* [mapping:soc] */
*libzephyr.a:lldesc.*(.literal .literal.* .text .text.*)
/* [mapping:log] */
*(.literal.esp_log_write .text.esp_log_write)
*(.literal.esp_log_timestamp .text.esp_log_timestamp)
*(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp)
*(.literal.esp_log_impl_lock .text.esp_log_impl_lock)
*(.literal.esp_log_impl_lock_timeout .text.esp_log_impl_lock_timeout)
*(.literal.esp_log_impl_unlock .text.esp_log_impl_unlock)
/* [mapping:spi_flash] */
*libzephyr.a:spi_flash_chip_boya.*(.literal .literal.* .text .text.*)
*libzephyr.a:spi_flash_chip_gd.*(.literal .literal.* .text .text.*)
*libzephyr.a:spi_flash_chip_generic.*(.literal .literal.* .text .text.*)
*libzephyr.a:spi_flash_chip_issi.*(.literal .literal.* .text .text.*)
*libzephyr.a:spi_flash_chip_mxic.*(.literal .literal.* .text .text.*)
*libzephyr.a:spi_flash_chip_mxic_opi.*(.literal .literal.* .text .text.*)
*libzephyr.a:spi_flash_chip_th.*(.literal .literal.* .text .text.*)
*libzephyr.a:spi_flash_chip_winbond.*(.literal .literal.* .text .text.*)
*libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*)
*libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*)
*libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*)
*libzephyr.a:spi_flash_hpm_enable.*(.literal .literal.* .text .text.*)
*libzephyr.a:spi_flash_oct_flash_init*(.literal .literal.* .text .text.*)
/* [mapping:esp_system] */
*libzephyr.a:esp_err.*(.literal .literal.* .text .text.*)
*(.literal.esp_system_abort .text.esp_system_abort)
/* [mapping:esp_hw_support] */
*(.literal.esp_cpu_stall .text.esp_cpu_stall)
*(.literal.esp_cpu_unstall .text.esp_cpu_unstall)
*(.literal.esp_cpu_reset .text.esp_cpu_reset)
*(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr)
*(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set)
*(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins)
*(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved)
*(.literal.rtc_vddsdio_get_config .text.rtc_vddsdio_get_config)
*(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config)
*libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*)
*libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*)
*libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*)
*libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*)
*libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*)
*libzephyr.a:systimer.*(.literal .literal.* .text .text.*)
*libzephyr.a:mspi_timing_config.*(.literal .literal.* .text .text.*)
*libzephyr.a:mspi_timing_tuning.*(.literal .literal.* .text .text.*)
*(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable)
/* [mapping:soc_pm] */
*(.literal.GPIO_HOLD_MASK .text.GPIO_HOLD_MASK)
/* [mapping:esp_rom] */
*libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*)
*libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*)
*libzephyr.a:esp_rom_wdt.*(.literal .literal.* .text .text.*)
/* [mapping:esp_mm] */
*libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*)
*libzephyr.a:cache_utils.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
*libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)
*libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
*libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
*libcoexist.a:(.wifi_slp_iram .wifi_slp_iram.*)
/* [mapping:esp_wifi] */
*(.literal.wifi_clock_enable_wrapper .text.wifi_clock_enable_wrapper)
*(.literal.wifi_clock_disable_wrapper .text.wifi_clock_disable_wrapper)
/* [mapping:esp_phy] */
*(.literal.esp_phy_enable .text.esp_phy_enable)
*(.literal.esp_phy_disable .text.esp_phy_disable)
*(.literal.esp_wifi_bt_power_domain_off .text.esp_wifi_bt_power_domain_off)
#endif /* CONFIG_ESP32_WIFI_IRAM_OPT */
#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
*libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
*libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
#endif /* CONFIG_ESP32_WIFI_RX_IRAM_OPT */
. = ALIGN(4) + 16;
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
#ifdef CONFIG_ESP_SIMPLE_BOOT
.loader.text :
{
. = ALIGN(4);
_loader_text_start = ABSOLUTE(.);
*libzephyr.a:bootloader_init.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_esp32c2.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_clock_init.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_wdt.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_flash_config_esp32c2.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_mem.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*)
*libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*)
*libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*)
*libzephyr.a:flash_ops.*(.literal .text .literal.* .text.*)
*libzephyr.a:flash_ops_esp32c2.*(.literal .text .literal.* .text.*)
*libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*)
*libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
*libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*)
*libzephyr.a:spi_flash_hal.*(.literal .literal.* .text .text.*)
*libzephyr.a:spi_flash_hal_common.*(.literal .literal.* .text .text.*)
*libzephyr.a:esp_flash_api.*(.literal .text .literal.* .text.*)
*libzephyr.a:esp_flash_spi_init.*(.literal .text .literal.* .text.*)
*libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*)
*libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*)
*libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*)
*libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*)
*libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*)
*libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*)
*libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
*libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
*libzephyr.a:cpu_region_protect.*(.literal .text .literal.* .text.*)
/* ??? */
*libzephyr.a:esp_gpio_reserve.*(.literal .text .literal.* .text.*)
. = ALIGN(0x10) + 0x10;
_loader_text_end = ABSOLUTE(.);
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
#endif /* CONFIG_ESP_SIMPLE_BOOT */
.iram0.text_end (NOLOAD) :
{
/* C2 memprot requires 512 B alignment for split lines */
. = ALIGN (16);
_iram_text_end = ABSOLUTE(.);
} GROUP_LINK_IN(IRAM_REGION)
.iram0.data :
{
. = ALIGN(16);
*(.iram.data)
*(.iram.data*)
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
.iram0.bss (NOLOAD) :
{
. = ALIGN(16);
*(.iram.bss)
*(.iram.bss*)
. = ALIGN(16);
_iram_end = ABSOLUTE(.);
} GROUP_LINK_IN(IRAM_REGION)
/* --- END OF IRAM --- */
/* --- START OF DRAM --- */
.dram0.dummy (NOLOAD):
{
/* Spacer section is required to skip .iram0.text area because
* iram0_0_seg and dram0_0_seg reflect the same address space on different buses.
*/
. = ORIGIN(dram0_0_seg) + MAX(_iram_end, user_iram_seg_org) - user_iram_seg_org;
. = ALIGN(16) + 16;
} GROUP_LINK_IN(RAMABLE_REGION)
.dram0.data :
{
. = ALIGN(4);
_data_start = ABSOLUTE(.);
__data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.data1)
#ifdef CONFIG_RISCV_GP
. = ALIGN(8);
__global_pointer$ = . + 0x800;
#endif /* CONFIG_RISCV_GP */
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
/* All dependent functions should be placed in DRAM to avoid issue
* when flash cache is disabled */
*libkernel.a:fatal.*(.rodata .rodata.* .srodata .srodata.*)
*libkernel.a:init.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:cbprintf_complete*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:log_core.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:log_backend_uart.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:log_output.*(.rodata .rodata.* .srodata .srodata.*)
*libdrivers__flash.a:flash_esp32.*(.rodata .rodata.* .srodata .srodata.*)
*libdrivers__serial.a:uart_esp32.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:periph_ctrl.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:loader.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:cache_utils.*(.rodata .rodata.* .srodata .srodata.*)
/* [mapping:hal] */
*libzephyr.a:mmu_hal.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:cache_hal.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:ledc_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:i2c_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:wdt_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:systimer_hal.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_hal_gpspi.*(.rodata .rodata.* .srodata .srodata.*)
/* [mapping:soc] */
*libzephyr.a:lldesc.*(.rodata .rodata.* .srodata .srodata.*)
/* [mapping:log] */
*(.rodata.esp_log_write)
*(.rodata.esp_log_timestamp)
*(.rodata.esp_log_early_timestamp)
*(.rodata.esp_log_impl_lock)
*(.rodata.esp_log_impl_lock_timeout)
*(.rodata.esp_log_impl_unlock)
/* [mapping:spi_flash] */
*libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_chip_mxic_opi.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:memspi_host_driver.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:flash_brownout_hook.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_wrap.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_hpm_enable.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_oct_flash_init.*(.rodata .rodata.* .srodata .srodata.*)
/* [mapping:esp_mm] */
*libzephyr.a:esp_cache.*(.rodata .rodata.* .srodata .srodata.*)
/* [mapping:esp_hw_support] */
*(.rodata.esp_cpu_stall)
*(.rodata.esp_cpu_unstall)
*(.rodata.esp_cpu_reset)
*(.rodata.esp_cpu_wait_for_intr)
*(.rodata.esp_cpu_compare_and_set)
*(.rodata.esp_gpio_reserve_pins)
*(.rodata.esp_gpio_is_pin_reserved)
*(.rodata.rtc_vddsdio_get_config)
*(.rodata.rtc_vddsdio_set_config)
*libzephyr.a:esp_memory_utils.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:rtc_clk.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:rtc_clk_init.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:systimer.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:mspi_timing_config.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:mspi_timing_tuning.*(.rodata .rodata.* .srodata .srodata.*)
*(.rodata.sar_periph_ctrl_power_enable)
/* [mapping:esp_system] */
*libzephyr.a:esp_err.*(.rodata .rodata.*)
*(.rodata.esp_system_abort)
. = ALIGN(4);
#include <snippets-rwdata.ld>
. = ALIGN(4);
KEEP(*(.jcr))
*(.dram1 .dram1.*)
. = ALIGN(4);
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
#ifdef CONFIG_ESP_SIMPLE_BOOT
/* Secondary loader sections */
.loader.data :
{
. = ALIGN(4);
_loader_data_start = ABSOLUTE(.);
*libzephyr.a:bootloader_soc.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:bootloader_init.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:bootloader_esp32c2.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:bootloader_clock_init.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:bootloader_wdt.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:bootloader_flash.*(.srodata .srodata.* .rodata .rodata.*)
*libzephyr.a:bootloader_flash_config_esp32c2.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:bootloader_clock_loader.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:bootloader_common_loader.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:bootloader_panic.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:cpu_region_protect.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:clk.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:esp_clk.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:flash_mmap.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:flash_ops.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:flash_ops_esp32c2.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:esp_gpio_reserve.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_hal.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:spi_flash_hal_common.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:esp_flash_api.*(.rodata .rodata.* .srodata .srodata.*)
*libzephyr.a:esp_flash_spi_init.*(.rodata .rodata.* .srodata .srodata.*)
. = ALIGN(16);
_loader_data_end = ABSOLUTE(.);
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
#endif /* CONFIG_ESP_SIMPLE_BOOT */
#include <snippets-data-sections.ld>
#include <zephyr/linker/common-ram.ld>
#include <snippets-ram-sections.ld>
#include <zephyr/linker/cplusplus-ram.ld>
/* logging sections should be placed in RAM area to avoid flash cache disabled issues */
#pragma push_macro("GROUP_ROM_LINK_IN")
#undef GROUP_ROM_LINK_IN
#define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN
#include <zephyr/linker/common-rom/common-rom-logging.ld>
#pragma pop_macro("GROUP_ROM_LINK_IN")
.dram0.end :
{
. = ALIGN(4);
_data_end = ABSOLUTE(.);
__data_end = ABSOLUTE(.);
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
.dram0.noinit (NOLOAD):
{
. = ALIGN(4);
*(.noinit)
*(.noinit.*)
. = ALIGN(4);
} GROUP_LINK_IN(RAMABLE_REGION)
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
__bss_start = ABSOLUTE(.);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.share.mem)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (16);
__bss_end = ABSOLUTE(.);
_bss_end = ABSOLUTE(.);
} GROUP_LINK_IN(RAMABLE_REGION)
/* Provide total SRAM usage, including IRAM and DRAM */
_image_ram_start = _iram_start - IRAM_DRAM_OFFSET;
#include <zephyr/linker/ram-end.ld>
ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")
/* --- END OF DRAM --- */
/* --- START OF .flash.text --- */
.flash.text_dummy (NOLOAD):
{
. = ALIGN(CACHE_ALIGN);
} GROUP_LINK_IN(ROMABLE_REGION)
/* Symbols used during the application memory mapping */
_image_irom_start = LOADADDR(.flash.text);
_image_irom_size = SIZEOF(.flash.text);
_image_irom_vaddr = ADDR(.flash.text);
.flash.text : ALIGN(CACHE_ALIGN)
{
_stext = .;
_instruction_reserved_start = ABSOLUTE(.);
_text_start = ABSOLUTE(.);
_instruction_reserved_start = ABSOLUTE(.);
__text_region_start = ABSOLUTE(.);
__rom_region_start = ABSOLUTE(.);
#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)
*libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
*libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*)
#endif /* CONFIG_ESP32_WIFI_IRAM_OPT */
#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
*libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
*libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*)
#endif /* CONFIG_ESP32_WIFI_RX_IRAM_OPT */
*(.literal .text .literal.* .text.*)
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
/* CPU will try to prefetch up to 16 bytes of
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
* safe access to up to 16 bytes after the last real instruction, add
* dummy bytes to ensure this
*/
. += 16;
_instruction_reserved_end = ABSOLUTE(.);
_text_end = ABSOLUTE(.);
_instruction_reserved_end = ABSOLUTE(.);
__text_region_end = ABSOLUTE(.);
__rom_region_end = ABSOLUTE(.);
_etext = .;
} GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)
/* --- END OF .flash.text --- */
/* --- START OF .rodata --- */
/* Align next section to 64k to allow mapping */
.flash.dummy (NOLOAD) :
{
. = ALIGN(CACHE_ALIGN);
} GROUP_LINK_IN(ROMABLE_REGION)
.flash.rodata_dummy (NOLOAD) :
{
/* Spacer in the IROM address to avoid interfering with the DROM address
* because DROM and IROM regions share the same address space */
. += SIZEOF(.flash.text);
. = ALIGN(CACHE_ALIGN);
} GROUP_LINK_IN(RODATA_REGION)
/* Symbols used during the application memory mapping */
_image_drom_start = LOADADDR(.flash.rodata);
_image_drom_size = _image_rodata_end - _image_rodata_start;
_image_drom_vaddr = ADDR(.flash.rodata);
.flash.rodata : ALIGN(0x10)
{
_rodata_reserved_start = ABSOLUTE(.);
_image_rodata_start = ABSOLUTE(.);
*(.rodata_desc .rodata_desc.*)
*(.rodata_custom_desc .rodata_custom_desc.*)
__rodata_region_start = ABSOLUTE(.);
. = ALIGN(4);
#include <snippets-rodata.ld>
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table .gcc_except_table.*)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
. = (. + 3) & ~ 3;
__eh_frame = ABSOLUTE(.);
KEEP(*(.eh_frame))
. = (. + 7) & ~ 3;
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
__rodata_region_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
*(.srodata)
*(.srodata.*)
*(.rodata)
*(.rodata.*)
*(.rodata_wlog)
*(.rodata_wlog*)
. = ALIGN(4);
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
#include <zephyr/linker/cplusplus-rom.ld>
#include <zephyr/linker/common-rom/common-rom-init.ld>
#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
#include <zephyr/linker/common-rom/common-rom-ztest.ld>
#include <zephyr/linker/common-rom/common-rom-net.ld>
#include <zephyr/linker/common-rom/common-rom-bt.ld>
#include <zephyr/linker/common-rom/common-rom-debug.ld>
#include <zephyr/linker/common-rom/common-rom-misc.ld>
#include <zephyr/linker/thread-local-storage.ld>
#include <snippets-sections.ld>
/* Create an explicit section at the end of all the data that shall be mapped into drom.
* This is used to calculate the size of the _image_drom_size variable */
.flash.rodata_end : ALIGN(0x10)
{
. = ALIGN(4);
#ifdef CONFIG_THREAD_LOCAL_STORAGE
/* create explicit symbol for __tdata_start so that it is loaded
* into proper DROM region atributted by AT keyword below
*/
__tdata_start = ADDR(tdata);
#endif
_rodata_reserved_end = ABSOLUTE(.);
_image_rodata_end = ABSOLUTE(.);
} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
/* --- END OF .rodata --- */
#ifdef CONFIG_GEN_ISR_TABLES
#include <zephyr/linker/intlist.ld>
#endif
#include <zephyr/linker/debug-sections.ld>
/DISCARD/ : { *(.note.GNU-stack) }
SECTION_PROLOGUE(.riscv.attributes, 0,)
{
KEEP(*(.riscv.attributes))
KEEP(*(.gnu.attributes))
}
}

291
soc/espressif/esp32c2/mcuboot.ld Normal file
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@ -0,0 +1,291 @@
/*
* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/linker/sections.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/linker/linker-tool.h>
#include "memory.h"
#ifdef CONFIG_XIP
#error "ESP32C2 bootloader cannot use XIP"
#endif /* CONFIG_XIP */
/* Disable all romable LMA */
#udef GROUP_DATA_LINK_IN
#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion
#define RAMABLE_REGION dram_seg
#define RODATA_REGION dram_seg
#define ROMABLE_REGION dram_seg
/* Global symbols required for espressif hal build */
MEMORY
{
iram_seg (RX) : org = BOOTLOADER_IRAM_SEG_START,
len = BOOTLOADER_IRAM_SEG_LEN
iram_loader_seg (RX) : org = BOOTLOADER_IRAM_LOADER_SEG_START,
len = BOOTLOADER_IRAM_LOADER_SEG_LEN
dram_seg (RW) : org = BOOTLOADER_DRAM_SEG_START,
len = BOOTLOADER_DRAM_SEG_LEN
#ifdef CONFIG_GEN_ISR_TABLES
IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
#endif
}
/* Default entry point: */
ENTRY(CONFIG_KERNEL_ENTRY)
SECTIONS
{
.iram0.loader_text :
{
. = ALIGN (16);
_loader_text_start = ABSOLUTE(.);
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
/* TODO: cross-segments calls in the libzephyr.a:device.* */
*libapp.a:flash_map_extended.*(.literal .text .literal.* .text.*)
*libzephyr.a:cbprintf_nano.*(.literal .text .literal.* .text.*)
*libzephyr.a:cpu.*(.literal .text .literal.* .text.*)
*libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
*libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*)
*libzephyr.a:flash_map.*(.literal .text .literal.* .text.*)
*libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*)
*libzephyr.a:heap.*(.literal .text .literal.* .text.*)
*libkernel.a:kheap.*(.literal .text .literal.* .text.*)
*libkernel.a:mempool.*(.literal .text .literal.* .text.*)
*(.literal.bootloader_mmap .text.bootloader_mmap)
*(.literal.bootloader_munmap .text.bootloader_munmap)
*libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*)
*libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
*(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*)
*(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler)
*(.literal.esp_log_timestamp .text.esp_log_timestamp)
*(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp)
*(.literal.esp_system_abort .text.esp_system_abort)
*(.fini.literal)
*(.fini)
*(.gnu.version)
_loader_text_end = ABSOLUTE(.);
_iram_end = ABSOLUTE(.);
} > iram_loader_seg
.iram0.text :
{
/* Vectors go to IRAM */
_iram_start = ABSOLUTE(.);
_init_start = ABSOLUTE(.);
__text_region_start = ABSOLUTE(.);
KEEP(*(.exception_vectors.text));
. = ALIGN(256);
_invalid_pc_placeholder = ABSOLUTE(.);
_iram_text_start = ABSOLUTE(.);
KEEP(*(.exception.entry*)); /* contains _isr_wrapper */
*(.exception.other*)
. = ALIGN(4);
*(.entry.text)
*(.init.literal)
*(.init)
. = ALIGN(4);
*(.iram1 .iram1.*)
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
/* C2 memprot requires 512 B alignment for split lines */
. = ALIGN (16);
_init_end = ABSOLUTE(.);
. = ALIGN(16);
*(.iram.data)
*(.iram.data*)
. = ALIGN(16);
*(.iram.bss)
*(.iram.bss*)
. = ALIGN(16);
*(.literal .text .literal.* .text.*)
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
/* CPU will try to prefetch up to 16 bytes of
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
* safe access to up to 16 bytes after the last real instruction, add
* dummy bytes to ensure this
*/
. += 16;
_text_end = ABSOLUTE(.);
__text_region_end = ABSOLUTE(.);
_etext = .;
/* Similar to _iram_start, this symbol goes here so it is
* resolved by addr2line in preference to the first symbol in
* the flash.text segment.
*/
_flash_cache_start = ABSOLUTE(0);
} > iram_seg
.dram0.data :
{
. = ALIGN(4);
__data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.data1)
#ifdef CONFIG_RISCV_GP
__global_pointer$ = . + 0x800;
#endif /* CONFIG_RISCV_GP */
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
*libzephyr.a:mmu_hal.*(.rodata .rodata.*)
*libzephyr.a:rtc_clk.*(.rodata .rodata.*)
KEEP(*(.jcr))
*(.dram1 .dram1.*)
. = ALIGN(4);
#include <snippets-rwdata.ld>
. = ALIGN(4);
*(.rodata_desc .rodata_desc.*)
*(.rodata_custom_desc .rodata_custom_desc.*)
. = ALIGN(4);
#include <snippets-rodata.ld>
. = ALIGN(4);
*(.rodata)
*(.rodata.*)
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table .gcc_except_table.*)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
. = (. + 3) & ~ 3;
__eh_frame = ABSOLUTE(.);
KEEP(*(.eh_frame))
. = (. + 7) & ~ 3;
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
__rodata_region_end = .;
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_thread_local_start = ABSOLUTE(.);
*(.tdata)
*(.tdata.*)
*(.tbss)
*(.tbss.*)
*(.srodata)
*(.srodata.*)
*(.rodata)
*(.rodata.*)
*(.rodata_wlog)
*(.rodata_wlog*)
_thread_local_end = ABSOLUTE(.);
/* _rodata_reserved_end = ABSOLUTE(.); */
. = ALIGN(4);
} > dram_seg
#include <zephyr/linker/common-rom/common-rom-init.ld>
#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
#include <zephyr/linker/common-rom/common-rom-debug.ld>
#include <zephyr/linker/common-rom/common-rom-misc.ld>
#include <snippets-sections.ld>
#include <zephyr/linker/cplusplus-rom.ld>
#include <zephyr/linker/thread-local-storage.ld>
#include <snippets-data-sections.ld>
#include <zephyr/linker/common-ram.ld>
#include <snippets-ram-sections.ld>
#include <zephyr/linker/cplusplus-ram.ld>
#include <zephyr/linker/common-rom/common-rom-logging.ld>
.noinit (NOLOAD):
{
. = ALIGN(4);
*(.noinit)
*(.noinit.*)
. = ALIGN(4);
} > dram_seg
/* Shared RAM */
.bss (NOLOAD):
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
__bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.share.mem)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
__bss_end = ABSOLUTE(.);
_bss_end = ABSOLUTE(.);
} > dram_seg
/* linker rel sections*/
#include <zephyr/linker/rel-sections.ld>
#ifdef CONFIG_GEN_ISR_TABLES
#include <zephyr/linker/intlist.ld>
#endif
#include <zephyr/linker/debug-sections.ld>
/DISCARD/ : { *(.note.GNU-stack) }
SECTION_PROLOGUE(.riscv.attributes, 0,)
{
KEEP(*(.riscv.attributes))
KEEP(*(.gnu.attributes))
}
}

69
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/*
* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/* SRAM0 (16kB) memory */
#define SRAM0_IRAM_START 0x4037c000
#define SRAM0_SIZE 0x4000
/* SRAM1 (256kB) memory */
#define SRAM1_DRAM_START 0x3fca0000
#define SRAM1_IRAM_START 0x40380000
/* ICache size is fixed to 16KB on ESP32-C2 */
#define ICACHE_SIZE SRAM0_SIZE
/** Simplified memory map for the bootloader.
* Make sure the bootloader can load into main memory without overwriting itself.
*
* ESP32-C2 ROM static data usage is as follows:
* - 0x3fccae00 - 0x3fcdc710: Shared buffers, used in UART/USB/SPI download mode only
* - 0x3fcdc710 - 0x3fcde710: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x3fcde710 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)
*
* The 2nd stage bootloader can take space up to the end of ROM shared
* buffers area (0x3fcdc710).
*/
/* The offset between Dbus and Ibus.
* Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses.
*/
#define IRAM_DRAM_OFFSET SRAM1_IRAM_START - SRAM1_DRAM_START
#define DRAM_BUFFERS_START 0x3fccae00
#define DRAM_STACK_START 0x3fcdc710
#define DRAM_ROM_BSS_DATA_START 0x3fcde710
/* Base address used for calculating memory layout
* counted from Dbus backwards and back to the Ibus
*/
#define BOOTLOADER_USER_DRAM_END DRAM_BUFFERS_START
/* For safety margin between bootloader data section and startup stacks */
#define BOOTLOADER_STACK_OVERHEAD 0x0
/* These lengths can be adjusted, if necessary: */
#define BOOTLOADER_DRAM_SEG_LEN 0x9800
#define BOOTLOADER_IRAM_SEG_LEN 0x9800
#define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x1400
/* Start of the lower region is determined by region size and the end of the higher region */
#define BOOTLOADER_IRAM_LOADER_SEG_END (BOOTLOADER_USER_DRAM_END + \
BOOTLOADER_STACK_OVERHEAD + IRAM_DRAM_OFFSET)
#define BOOTLOADER_IRAM_LOADER_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_END - \
BOOTLOADER_IRAM_LOADER_SEG_LEN)
#define BOOTLOADER_IRAM_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN)
#define BOOTLOADER_DRAM_SEG_START (BOOTLOADER_IRAM_SEG_START - IRAM_DRAM_OFFSET - \
BOOTLOADER_DRAM_SEG_LEN)
/* Flash */
#ifdef CONFIG_FLASH_SIZE
#define FLASH_SIZE CONFIG_FLASH_SIZE
#else
#define FLASH_SIZE 0x400000
#endif
/* Cached memory */
#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE
#define IROM_SEG_ORG 0x42000000
#define IROM_SEG_LEN FLASH_SIZE
#define DROM_SEG_ORG 0x3c000000
#define DROM_SEG_LEN FLASH_SIZE

78
soc/espressif/esp32c2/pinctrl_soc.h Normal file
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/*
* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* ESP32C2 SoC specific helpers for pinctrl driver
*/
#ifndef ZEPHYR_SOC_RISCV_ESP32C2_PINCTRL_SOC_H_
#define ZEPHYR_SOC_RISCV_ESP32C2_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
/** @cond INTERNAL_HIDDEN */
/** Type for ESP32 pin. */
typedef struct pinctrl_soc_pin {
/** Pinmux settings (pin, direction and signal). */
uint32_t pinmux;
/** Pincfg settings (bias). */
uint32_t pincfg;
} pinctrl_soc_pin_t;
/**
* @brief Utility macro to initialize pinmux field in #pinctrl_pin_t.
*
* @param node_id Node identifier.
*/
#define Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx) DT_PROP_BY_IDX(node_id, prop, idx)
/**
* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
*
* @param node_id Node identifier.
*/
#define Z_PINCTRL_ESP32_PINCFG_INIT(node_id) \
(((ESP32_NO_PULL * DT_PROP(node_id, bias_disable)) << ESP32_PIN_BIAS_SHIFT) | \
((ESP32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << ESP32_PIN_BIAS_SHIFT) | \
((ESP32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << ESP32_PIN_BIAS_SHIFT) | \
((ESP32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << ESP32_PIN_DRV_SHIFT) | \
((ESP32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << ESP32_PIN_DRV_SHIFT) | \
((ESP32_PIN_OUT_HIGH * DT_PROP(node_id, output_high)) << ESP32_PIN_OUT_SHIFT) | \
((ESP32_PIN_OUT_LOW * DT_PROP(node_id, output_low)) << ESP32_PIN_OUT_SHIFT) | \
((ESP32_PIN_OUT_EN * DT_PROP(node_id, output_enable)) << ESP32_PIN_EN_DIR_SHIFT) | \
((ESP32_PIN_IN_EN * DT_PROP(node_id, input_enable)) << ESP32_PIN_EN_DIR_SHIFT))
/**
* @brief Utility macro to initialize each pin.
*
* @param node_id Node identifier.
* @param prop Property name.
* @param idx Property entry index.
*/
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
{.pinmux = Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx), \
.pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)},
/**
* @brief Utility macro to initialize state pins contained in a given property.
*
* @param node_id Node identifier.
* @param prop Property name describing state pins.
*/
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{ \
DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
Z_PINCTRL_STATE_PIN_INIT) \
}
/** @endcond */
#endif /* ZEPHYR_SOC_RISCV_ESP32C2_PINCTRL_SOC_H_ */

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/*
* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Include esp-idf headers first to avoid redefining BIT() macro */
#include <soc/rtc_cntl_reg.h>
#include <soc/timer_group_reg.h>
#include <soc/ext_mem_defs.h>
#include <soc/gpio_reg.h>
#include <soc/syscon_reg.h>
#include <soc/system_reg.h>
#include "hal/wdt_hal.h"
#include "esp_cpu.h"
#include "hal/soc_hal.h"
#include "hal/cpu_hal.h"
#include "esp_timer.h"
#include "esp_private/system_internal.h"
#include "esp_clk_internal.h"
#include <soc/interrupt_reg.h>
#include <esp_private/spi_flash_os.h>
#include "esp_private/esp_mmu_map_private.h"
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
#include <zephyr/kernel_structs.h>
#include <kernel_internal.h>
#include <string.h>
#include <zephyr/toolchain.h>
#include <soc.h>
extern void esp_reset_reason_init(void);
/*
* This is written in C rather than assembly since, during the port bring up,
* Zephyr is being booted by the Espressif bootloader. With it, the C stack
* is already set up.
*/
void __attribute__((section(".iram1"))) __esp_platform_start(void)
{
__asm__ __volatile__("la t0, _esp32c2_vector_table\n"
"csrw mtvec, t0\n");
z_bss_zero();
/* Disable normal interrupts. */
csr_read_clear(mstatus, MSTATUS_MIE);
esp_reset_reason_init();
#ifndef CONFIG_MCUBOOT
/* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
* related issues in application. Hence disable that as we are about to start
* Zephyr environment.
*/
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
wdt_hal_disable(&rtc_wdt_ctx);
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
/* Enable wireless phy subsystem clock,
* This needs to be done before the kernel starts
*/
REG_CLR_BIT(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_SDIOSLAVE_EN);
SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
#ifdef CONFIG_SOC_FLASH_ESP32
esp_mspi_pin_init();
/**
* This function initialise the Flash chip to the user-defined settings.
*
* In bootloader, we only init Flash (and MSPI) to a preliminary
* state, for being flexible to different chips.
* In this stage, we re-configure the Flash (and MSPI) to required configuration
*/
spi_flash_init_chip_state();
esp_mmu_map_init();
#endif /*CONFIG_SOC_FLASH_ESP32*/
esp_timer_early_init();
#if CONFIG_SOC_FLASH_ESP32
spi_flash_guard_set(&g_flash_guard_default_ops);
#endif
#endif /* !CONFIG_MCUBOOT */
/*Initialize the esp32c2 interrupt controller */
esp_intr_initialize();
/* Start Zephyr */
z_cstart();
CODE_UNREACHABLE;
}
/* Boot-time static default printk handler, possibly to be overridden later. */
int IRAM_ATTR arch_printk_char_out(int c)
{
if (c == '\n') {
esp_rom_uart_tx_one_char('\r');
}
esp_rom_uart_tx_one_char(c);
return 0;
}
void sys_arch_reboot(int type)
{
esp_restart_noos();
}

56
soc/espressif/esp32c2/soc.h Normal file
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/*
* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __SOC_H__
#define __SOC_H__
#ifndef _ASMLANGUAGE
#include <soc/soc.h>
#include <rom/ets_sys.h>
#include <rom/spi_flash.h>
#include <zephyr/types.h>
#include <stdbool.h>
#include <esp_private/esp_clk.h>
#endif
#ifndef _ASMLANGUAGE
void __esp_platform_start(void);
static inline uint32_t esp_core_id(void)
{
return 0;
}
extern void esp_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
extern void esp_rom_uart_attach(void);
extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no);
extern int esp_rom_uart_tx_one_char(uint8_t chr);
extern int esp_rom_uart_rx_one_char(uint8_t *chr);
extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index, bool inverted);
extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
bool out_invrted, bool out_enabled_inverted);
extern void esp_rom_ets_set_user_start(uint32_t start);
extern void esprv_intc_int_set_threshold(int priority_threshold);
uint32_t soc_intr_get_next_source(void);
extern void esp_rom_Cache_Resume_ICache(uint32_t autoload);
extern int esp_rom_Cache_Invalidate_Addr(uint32_t addr, uint32_t size);
extern uint32_t esp_rom_Cache_Suspend_ICache(void);
extern void esp_rom_Cache_Invalidate_ICache_All(void);
extern int esp_rom_Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,
uint32_t psize, uint32_t num, uint32_t fixed);
extern int esp_rom_Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,
uint32_t psize, uint32_t num, uint32_t fixed);
extern void esp_rom_Cache_Resume_ICache(uint32_t autoload);
extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index,
bool inverted);
extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
bool out_inverted,
bool out_enabled_inverted);
#endif /* _ASMLANGUAGE */
#endif /* __SOC_H__ */

20
soc/espressif/esp32c2/soc_irq.S Normal file
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/* Copyright 2024 Espressif Systems (Shanghai) PTE LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/offsets.h>
#include <zephyr/toolchain.h>
/* Exports */
GTEXT(__soc_handle_irq)
GTEXT(soc_intr_get_next_source)
SECTION_FUNC(exception.other, __soc_handle_irq)
addi sp, sp,-4
sw ra, 0x00(sp)
la t1, soc_intr_get_next_source
jalr ra, t1, 0
lw ra, 0x00(sp)
addi sp, sp, 4
ret

69
soc/espressif/esp32c2/soc_irq.c Normal file
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/*
* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc/rtc_cntl_reg.h>
#include <soc/timer_group_reg.h>
#include <soc/ext_mem_defs.h>
#include <soc/gpio_reg.h>
#include <soc/syscon_reg.h>
#include <soc/system_reg.h>
#include <riscv/interrupt.h>
#include <soc/interrupt_reg.h>
#include <soc/periph_defs.h>
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
#include <zephyr/kernel_structs.h>
#include <string.h>
#include <zephyr/toolchain.h>
#include <soc.h>
#include <zephyr/arch/riscv/arch.h>
#define ESP32C2_INTSTATUS_SLOT1_THRESHOLD 32
void arch_irq_enable(unsigned int irq)
{
esp_intr_enable(irq);
}
void arch_irq_disable(unsigned int irq)
{
esp_intr_disable(irq);
}
int arch_irq_is_enabled(unsigned int irq)
{
bool res = false;
uint32_t key = irq_lock();
if (irq < 32) {
res = esp_intr_get_enabled_intmask(0) & BIT(irq);
} else {
res = esp_intr_get_enabled_intmask(1) & BIT(irq - 32);
}
irq_unlock(key);
return res;
}
uint32_t soc_intr_get_next_source(void)
{
uint32_t status;
uint32_t source;
status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_REG_0_REG) &
esp_intr_get_enabled_intmask(0);
if (status) {
source = __builtin_ffs(status) - 1;
} else {
status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_REG_1_REG) &
esp_intr_get_enabled_intmask(1);
source = (__builtin_ffs(status) - 1 + ESP32C2_INTSTATUS_SLOT1_THRESHOLD);
}
return source;
}

35
soc/espressif/esp32c2/vectors.S Normal file
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/* Copyright 2024 Espressif Systems (Shanghai) PTE LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/interrupt_reg.h"
#include "riscv/rvruntime-frames.h"
#include "soc/soc_caps.h"
#include <zephyr/toolchain.h>
/* Imports */
GTEXT(_isr_wrapper)
/* This is the vector table. MTVEC points here.
*
* Use 4-byte intructions here. 1 instruction = 1 entry of the table.
* The CPU jumps to MTVEC (i.e. the first entry) in case of an exception,
* and (MTVEC & 0xfffffffc) + (mcause & 0x7fffffff) * 4, in case of an interrupt.
*
* Note: for our CPU, we need to place this on a 256-byte boundary, as CPU
* only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
*/
.global _esp32c2_vector_table
.section .exception_vectors.text
.balign 0x100
.type _esp32c2_vector_table, @function
_esp32c2_vector_table:
.option push
.option norvc
.rept (32)
j _isr_wrapper /* 32 identical entries, all pointing to the interrupt handler */
.endr

3
soc/espressif/soc.yml
View file

@ -16,6 +16,9 @@ family:
cpuclusters:
- name: procpu
- name: appcpu
- name: esp32c2
socs:
- name: esp32c2
- name: esp32c3
socs:
- name: esp32c3