fad55d18ad
Files for SoC support: ESP32C2 and ESP8684 (same core). Basic device tree configuration. Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
69 lines
2.6 KiB
C
69 lines
2.6 KiB
C
/*
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* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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/* SRAM0 (16kB) memory */
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#define SRAM0_IRAM_START 0x4037c000
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#define SRAM0_SIZE 0x4000
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/* SRAM1 (256kB) memory */
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#define SRAM1_DRAM_START 0x3fca0000
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#define SRAM1_IRAM_START 0x40380000
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/* ICache size is fixed to 16KB on ESP32-C2 */
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#define ICACHE_SIZE SRAM0_SIZE
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/** Simplified memory map for the bootloader.
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* Make sure the bootloader can load into main memory without overwriting itself.
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*
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* ESP32-C2 ROM static data usage is as follows:
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* - 0x3fccae00 - 0x3fcdc710: Shared buffers, used in UART/USB/SPI download mode only
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* - 0x3fcdc710 - 0x3fcde710: PRO CPU stack, can be reclaimed as heap after RTOS startup
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* - 0x3fcde710 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)
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*
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* The 2nd stage bootloader can take space up to the end of ROM shared
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* buffers area (0x3fcdc710).
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*/
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/* The offset between Dbus and Ibus.
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* Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses.
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*/
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#define IRAM_DRAM_OFFSET SRAM1_IRAM_START - SRAM1_DRAM_START
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#define DRAM_BUFFERS_START 0x3fccae00
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#define DRAM_STACK_START 0x3fcdc710
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#define DRAM_ROM_BSS_DATA_START 0x3fcde710
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/* Base address used for calculating memory layout
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* counted from Dbus backwards and back to the Ibus
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*/
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#define BOOTLOADER_USER_DRAM_END DRAM_BUFFERS_START
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/* For safety margin between bootloader data section and startup stacks */
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#define BOOTLOADER_STACK_OVERHEAD 0x0
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/* These lengths can be adjusted, if necessary: */
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#define BOOTLOADER_DRAM_SEG_LEN 0x9800
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#define BOOTLOADER_IRAM_SEG_LEN 0x9800
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#define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x1400
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/* Start of the lower region is determined by region size and the end of the higher region */
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#define BOOTLOADER_IRAM_LOADER_SEG_END (BOOTLOADER_USER_DRAM_END + \
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BOOTLOADER_STACK_OVERHEAD + IRAM_DRAM_OFFSET)
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#define BOOTLOADER_IRAM_LOADER_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_END - \
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BOOTLOADER_IRAM_LOADER_SEG_LEN)
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#define BOOTLOADER_IRAM_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN)
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#define BOOTLOADER_DRAM_SEG_START (BOOTLOADER_IRAM_SEG_START - IRAM_DRAM_OFFSET - \
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BOOTLOADER_DRAM_SEG_LEN)
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/* Flash */
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#ifdef CONFIG_FLASH_SIZE
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#define FLASH_SIZE CONFIG_FLASH_SIZE
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#else
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#define FLASH_SIZE 0x400000
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#endif
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/* Cached memory */
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#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE
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#define IROM_SEG_ORG 0x42000000
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#define IROM_SEG_LEN FLASH_SIZE
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#define DROM_SEG_ORG 0x3c000000
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#define DROM_SEG_LEN FLASH_SIZE
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