boards: riscv32: add LiteX VexRiscV board

Add LiteX VexRiscV board platform definitions and
default configurations.

Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>

boards/riscv32/litex_vexriscv/CMakeLists.txt

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+#
+# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)

boards/riscv32/litex_vexriscv/Kconfig.board

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+#
+# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_LITEX_VEXRISCV
+	bool "Board with LiteX/VexRiscV CPU"
+	depends on SOC_RISCV32_LITEX_VEXRISCV

boards/riscv32/litex_vexriscv/Kconfig.defconfig

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+#
+# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_LITEX_VEXRISCV
+
+config BOARD
+	default "litex_vexriscv"
+
+endif

boards/riscv32/litex_vexriscv/doc/litex_vexriscv.rst

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+.. _litex-vexriscv:
+
+LiteX VexRiscv
+##############
+
+Overview
+********
+
+LiteX is a Migen-based System on Chip, supporting various softcore CPUs,
+including VexRiscv. The LiteX SoC with VexRiscv CPU can be deployed on e.g.
+Digilent ARTY board. More information can be found on:
+`LiteX's website <https://github.com/enjoy-digital/litex>`_ and
+`VexRiscv's website <https://github.com/SpinalHDL/VexRiscv>`_.
+
+Programming and debugging
+*************************
+
+Building
+========
+
+Applications for the ``litex_vexriscv`` board configuration can be built as usual
+(see :ref:`build_an_application`).
+In order to build the application for ``litex_vexriscv``, set the ``BOARD`` variable
+to ``litex_vexriscv``.
+
+Booting
+=======
+
+You can boot from serial port using `flterm: <https://github.com/timvideos/flterm>`_, e.g.:
+
+.. code-block:: bash
+
+    flterm --port /dev/ttyUSB0 --kernel <path_to_zephyr.bin> --kernel-adr 0x40000000

boards/riscv32/litex_vexriscv/litex_vexriscv.dts

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+/*
+ * Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <riscv32-litex-vexriscv.dtsi>
+
+/ {
+	model = "LiteX VexRiscV";
+	compatible = "litex,vexriscv";
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,timer = &timer0;
+		zephyr,sram = &ram0;
+	};
+
+	ram0: memory@40000000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x40000000 0x10000000>;
+	};
+};
+
+&uart0 {
+	status = "ok";
+	current-speed = <115200>;
+};
+
+&timer0 {
+	status = "ok";
+};

boards/riscv32/litex_vexriscv/litex_vexriscv.yaml

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+#
+# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+---
+identifier: litex_vexriscv
+name: LiteX SoC with VexRiscV softcore CPU
+type: mcu
+arch: riscv32
+toolchain:
+  - zephyr
+ram: 262144
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+    - xip

boards/riscv32/litex_vexriscv/litex_vexriscv_defconfig

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+#
+# Copyright (c) 2019 Antmicro <www.antmicro.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_RISCV32=y
+CONFIG_SOC_RISCV32_LITEX_VEXRISCV=y
+CONFIG_BOARD_LITEX_VEXRISCV=y
+CONFIG_VEXRISCV_LITEX_IRQ=y
+CONFIG_LITEX_TIMER=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_LITEUART=y
+CONFIG_UART_LITEUART_PORT_0=y
+CONFIG_UART_CONSOLE=y