From f9efca4b4f3ee81a1e36646ab52a020c5e2d14da Mon Sep 17 00:00:00 2001 From: Filip Kokosinski Date: Thu, 28 Mar 2019 14:50:13 +0100 Subject: [PATCH] boards: riscv32: add LiteX VexRiscV board Add LiteX VexRiscV board platform definitions and default configurations. Signed-off-by: Filip Kokosinski Signed-off-by: Mateusz Holenko --- boards/riscv32/litex_vexriscv/CMakeLists.txt | 7 ++++ boards/riscv32/litex_vexriscv/Kconfig.board | 9 +++++ .../riscv32/litex_vexriscv/Kconfig.defconfig | 12 +++++++ .../litex_vexriscv/doc/litex_vexriscv.rst | 33 +++++++++++++++++ .../riscv32/litex_vexriscv/litex_vexriscv.dts | 35 +++++++++++++++++++ .../litex_vexriscv/litex_vexriscv.yaml | 18 ++++++++++ .../litex_vexriscv/litex_vexriscv_defconfig | 16 +++++++++ 7 files changed, 130 insertions(+) create mode 100644 boards/riscv32/litex_vexriscv/CMakeLists.txt create mode 100644 boards/riscv32/litex_vexriscv/Kconfig.board create mode 100644 boards/riscv32/litex_vexriscv/Kconfig.defconfig create mode 100644 boards/riscv32/litex_vexriscv/doc/litex_vexriscv.rst create mode 100644 boards/riscv32/litex_vexriscv/litex_vexriscv.dts create mode 100644 boards/riscv32/litex_vexriscv/litex_vexriscv.yaml create mode 100644 boards/riscv32/litex_vexriscv/litex_vexriscv_defconfig diff --git a/boards/riscv32/litex_vexriscv/CMakeLists.txt b/boards/riscv32/litex_vexriscv/CMakeLists.txt new file mode 100644 index 00000000000..a9ee4b410b6 --- /dev/null +++ b/boards/riscv32/litex_vexriscv/CMakeLists.txt @@ -0,0 +1,7 @@ +# +# Copyright (c) 2018 - 2019 Antmicro +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers) diff --git a/boards/riscv32/litex_vexriscv/Kconfig.board b/boards/riscv32/litex_vexriscv/Kconfig.board new file mode 100644 index 00000000000..b84b1e6a134 --- /dev/null +++ b/boards/riscv32/litex_vexriscv/Kconfig.board @@ -0,0 +1,9 @@ +# +# Copyright (c) 2018 - 2019 Antmicro +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_LITEX_VEXRISCV + bool "Board with LiteX/VexRiscV CPU" + depends on SOC_RISCV32_LITEX_VEXRISCV diff --git a/boards/riscv32/litex_vexriscv/Kconfig.defconfig b/boards/riscv32/litex_vexriscv/Kconfig.defconfig new file mode 100644 index 00000000000..a8650f49cca --- /dev/null +++ b/boards/riscv32/litex_vexriscv/Kconfig.defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2018 - 2019 Antmicro +# +# SPDX-License-Identifier: Apache-2.0 +# + +if BOARD_LITEX_VEXRISCV + +config BOARD + default "litex_vexriscv" + +endif diff --git a/boards/riscv32/litex_vexriscv/doc/litex_vexriscv.rst b/boards/riscv32/litex_vexriscv/doc/litex_vexriscv.rst new file mode 100644 index 00000000000..d602a791a11 --- /dev/null +++ b/boards/riscv32/litex_vexriscv/doc/litex_vexriscv.rst @@ -0,0 +1,33 @@ +.. _litex-vexriscv: + +LiteX VexRiscv +############## + +Overview +******** + +LiteX is a Migen-based System on Chip, supporting various softcore CPUs, +including VexRiscv. The LiteX SoC with VexRiscv CPU can be deployed on e.g. +Digilent ARTY board. More information can be found on: +`LiteX's website `_ and +`VexRiscv's website `_. + +Programming and debugging +************************* + +Building +======== + +Applications for the ``litex_vexriscv`` board configuration can be built as usual +(see :ref:`build_an_application`). +In order to build the application for ``litex_vexriscv``, set the ``BOARD`` variable +to ``litex_vexriscv``. + +Booting +======= + +You can boot from serial port using `flterm: `_, e.g.: + +.. code-block:: bash + + flterm --port /dev/ttyUSB0 --kernel --kernel-adr 0x40000000 diff --git a/boards/riscv32/litex_vexriscv/litex_vexriscv.dts b/boards/riscv32/litex_vexriscv/litex_vexriscv.dts new file mode 100644 index 00000000000..7944c822fd9 --- /dev/null +++ b/boards/riscv32/litex_vexriscv/litex_vexriscv.dts @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2018 - 2019 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "LiteX VexRiscV"; + compatible = "litex,vexriscv"; + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,timer = &timer0; + zephyr,sram = &ram0; + }; + + ram0: memory@40000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x40000000 0x10000000>; + }; +}; + +&uart0 { + status = "ok"; + current-speed = <115200>; +}; + +&timer0 { + status = "ok"; +}; diff --git a/boards/riscv32/litex_vexriscv/litex_vexriscv.yaml b/boards/riscv32/litex_vexriscv/litex_vexriscv.yaml new file mode 100644 index 00000000000..a28bb7c5343 --- /dev/null +++ b/boards/riscv32/litex_vexriscv/litex_vexriscv.yaml @@ -0,0 +1,18 @@ +# +# Copyright (c) 2018 - 2019 Antmicro +# +# SPDX-License-Identifier: Apache-2.0 +# +--- +identifier: litex_vexriscv +name: LiteX SoC with VexRiscV softcore CPU +type: mcu +arch: riscv32 +toolchain: + - zephyr +ram: 262144 +testing: + ignore_tags: + - net + - bluetooth + - xip diff --git a/boards/riscv32/litex_vexriscv/litex_vexriscv_defconfig b/boards/riscv32/litex_vexriscv/litex_vexriscv_defconfig new file mode 100644 index 00000000000..c9d5a53b95a --- /dev/null +++ b/boards/riscv32/litex_vexriscv/litex_vexriscv_defconfig @@ -0,0 +1,16 @@ +# +# Copyright (c) 2019 Antmicro +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_RISCV32=y +CONFIG_SOC_RISCV32_LITEX_VEXRISCV=y +CONFIG_BOARD_LITEX_VEXRISCV=y +CONFIG_VEXRISCV_LITEX_IRQ=y +CONFIG_LITEX_TIMER=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_LITEUART=y +CONFIG_UART_LITEUART_PORT_0=y +CONFIG_UART_CONSOLE=y