boards: riscv32: add LiteX VexRiscV board
Add LiteX VexRiscV board platform definitions and default configurations. Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
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boards/riscv32/litex_vexriscv/CMakeLists.txt
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boards/riscv32/litex_vexriscv/CMakeLists.txt
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#
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# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
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boards/riscv32/litex_vexriscv/Kconfig.board
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boards/riscv32/litex_vexriscv/Kconfig.board
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#
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# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config BOARD_LITEX_VEXRISCV
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bool "Board with LiteX/VexRiscV CPU"
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depends on SOC_RISCV32_LITEX_VEXRISCV
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boards/riscv32/litex_vexriscv/Kconfig.defconfig
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boards/riscv32/litex_vexriscv/Kconfig.defconfig
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#
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# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if BOARD_LITEX_VEXRISCV
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config BOARD
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default "litex_vexriscv"
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endif
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boards/riscv32/litex_vexriscv/doc/litex_vexriscv.rst
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boards/riscv32/litex_vexriscv/doc/litex_vexriscv.rst
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.. _litex-vexriscv:
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LiteX VexRiscv
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##############
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Overview
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********
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LiteX is a Migen-based System on Chip, supporting various softcore CPUs,
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including VexRiscv. The LiteX SoC with VexRiscv CPU can be deployed on e.g.
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Digilent ARTY board. More information can be found on:
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`LiteX's website <https://github.com/enjoy-digital/litex>`_ and
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`VexRiscv's website <https://github.com/SpinalHDL/VexRiscv>`_.
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Programming and debugging
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*************************
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Building
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========
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Applications for the ``litex_vexriscv`` board configuration can be built as usual
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(see :ref:`build_an_application`).
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In order to build the application for ``litex_vexriscv``, set the ``BOARD`` variable
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to ``litex_vexriscv``.
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Booting
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=======
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You can boot from serial port using `flterm: <https://github.com/timvideos/flterm>`_, e.g.:
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.. code-block:: bash
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flterm --port /dev/ttyUSB0 --kernel <path_to_zephyr.bin> --kernel-adr 0x40000000
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boards/riscv32/litex_vexriscv/litex_vexriscv.dts
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boards/riscv32/litex_vexriscv/litex_vexriscv.dts
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/*
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* Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <riscv32-litex-vexriscv.dtsi>
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/ {
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model = "LiteX VexRiscV";
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compatible = "litex,vexriscv";
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,timer = &timer0;
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zephyr,sram = &ram0;
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};
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ram0: memory@40000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x40000000 0x10000000>;
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};
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};
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&uart0 {
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status = "ok";
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current-speed = <115200>;
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};
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&timer0 {
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status = "ok";
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};
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boards/riscv32/litex_vexriscv/litex_vexriscv.yaml
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boards/riscv32/litex_vexriscv/litex_vexriscv.yaml
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#
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# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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---
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identifier: litex_vexriscv
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name: LiteX SoC with VexRiscV softcore CPU
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type: mcu
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arch: riscv32
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toolchain:
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- zephyr
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ram: 262144
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testing:
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ignore_tags:
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- net
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- bluetooth
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- xip
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boards/riscv32/litex_vexriscv/litex_vexriscv_defconfig
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boards/riscv32/litex_vexriscv/litex_vexriscv_defconfig
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#
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# Copyright (c) 2019 Antmicro <www.antmicro.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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CONFIG_RISCV32=y
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CONFIG_SOC_RISCV32_LITEX_VEXRISCV=y
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CONFIG_BOARD_LITEX_VEXRISCV=y
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CONFIG_VEXRISCV_LITEX_IRQ=y
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CONFIG_LITEX_TIMER=y
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_LITEUART=y
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CONFIG_UART_LITEUART_PORT_0=y
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CONFIG_UART_CONSOLE=y
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