arch: aarch32: document exception priority scheme for 32-bit ARM
This commit adds some documentation for the exception priority scheme for 32-bit ARM architecture variants. In addition we document that SVCall priority level for ARMv6-M is implicitly set to highest (by leaving it as default). Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
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@ -88,6 +88,9 @@ static ALWAYS_INLINE void z_arm_exc_setup(void)
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NVIC_SetPriority(PendSV_IRQn, 0xff);
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#ifdef CONFIG_CPU_CORTEX_M_HAS_BASEPRI
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/* Note: SVCall IRQ priority level is left to default (0)
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* for Cortex-M variants without BASEPRI (e.g. ARMv6-M).
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*/
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NVIC_SetPriority(SVCall_IRQn, _EXC_SVC_PRIO);
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#endif
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@ -17,6 +17,22 @@
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/* for assembler, only works with constants */
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#define Z_EXC_PRIO(pri) (((pri) << (8 - DT_NUM_IRQ_PRIO_BITS)) & 0xff)
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/*
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* In architecture variants with non-programmable fault exceptions
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* (e.g. Cortex-M Baseline variants), hardware ensures processor faults
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* are given the highest interrupt priority level. SVCalls are assigned
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* the highest configurable priority level (level 0); note, however, that
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* this interrupt level may be shared with HW interrupts.
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*
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* In Cortex variants with programmable fault exception priorities we
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* assign the highest interrupt priority level (level 0) to processor faults
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* with configurable priority.
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* The highest priority level may be shared with either Zero-Latency IRQs (if
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* support for the feature is enabled) or with SVCall priority level.
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* Regular HW IRQs are always assigned priority levels lower than the priority
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* levels for SVCalls, Zero-Latency IRQs and processor faults.
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*
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*/
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#if defined(CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS)
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#define _EXCEPTION_RESERVED_PRIO 1
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#else
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