arch: aarch32: document exception priority scheme for 32-bit ARM

This commit adds some documentation for the exception
priority scheme for 32-bit ARM architecture variants.
In addition we document that SVCall priority level for
ARMv6-M is implicitly set to highest (by leaving it as
default).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit is contained in:
Ioannis Glaropoulos 2020-02-10 17:03:27 +01:00 committed by Andrew Boie
commit f9d9b7642e
2 changed files with 19 additions and 0 deletions

View file

@ -88,6 +88,9 @@ static ALWAYS_INLINE void z_arm_exc_setup(void)
NVIC_SetPriority(PendSV_IRQn, 0xff);
#ifdef CONFIG_CPU_CORTEX_M_HAS_BASEPRI
/* Note: SVCall IRQ priority level is left to default (0)
* for Cortex-M variants without BASEPRI (e.g. ARMv6-M).
*/
NVIC_SetPriority(SVCall_IRQn, _EXC_SVC_PRIO);
#endif

View file

@ -17,6 +17,22 @@
/* for assembler, only works with constants */
#define Z_EXC_PRIO(pri) (((pri) << (8 - DT_NUM_IRQ_PRIO_BITS)) & 0xff)
/*
* In architecture variants with non-programmable fault exceptions
* (e.g. Cortex-M Baseline variants), hardware ensures processor faults
* are given the highest interrupt priority level. SVCalls are assigned
* the highest configurable priority level (level 0); note, however, that
* this interrupt level may be shared with HW interrupts.
*
* In Cortex variants with programmable fault exception priorities we
* assign the highest interrupt priority level (level 0) to processor faults
* with configurable priority.
* The highest priority level may be shared with either Zero-Latency IRQs (if
* support for the feature is enabled) or with SVCall priority level.
* Regular HW IRQs are always assigned priority levels lower than the priority
* levels for SVCalls, Zero-Latency IRQs and processor faults.
*
*/
#if defined(CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS)
#define _EXCEPTION_RESERVED_PRIO 1
#else