From f9d9b7642e1691ca17ccb74e23807392d9005e3d Mon Sep 17 00:00:00 2001 From: Ioannis Glaropoulos Date: Mon, 10 Feb 2020 17:03:27 +0100 Subject: [PATCH] arch: aarch32: document exception priority scheme for 32-bit ARM This commit adds some documentation for the exception priority scheme for 32-bit ARM architecture variants. In addition we document that SVCall priority level for ARMv6-M is implicitly set to highest (by leaving it as default). Signed-off-by: Ioannis Glaropoulos --- arch/arm/include/aarch32/cortex_m/exc.h | 3 +++ include/arch/arm/aarch32/exc.h | 16 ++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm/include/aarch32/cortex_m/exc.h b/arch/arm/include/aarch32/cortex_m/exc.h index 355782e6c2f..0063bce9a92 100644 --- a/arch/arm/include/aarch32/cortex_m/exc.h +++ b/arch/arm/include/aarch32/cortex_m/exc.h @@ -88,6 +88,9 @@ static ALWAYS_INLINE void z_arm_exc_setup(void) NVIC_SetPriority(PendSV_IRQn, 0xff); #ifdef CONFIG_CPU_CORTEX_M_HAS_BASEPRI + /* Note: SVCall IRQ priority level is left to default (0) + * for Cortex-M variants without BASEPRI (e.g. ARMv6-M). + */ NVIC_SetPriority(SVCall_IRQn, _EXC_SVC_PRIO); #endif diff --git a/include/arch/arm/aarch32/exc.h b/include/arch/arm/aarch32/exc.h index 9d519d7545f..ba63fc888a1 100644 --- a/include/arch/arm/aarch32/exc.h +++ b/include/arch/arm/aarch32/exc.h @@ -17,6 +17,22 @@ /* for assembler, only works with constants */ #define Z_EXC_PRIO(pri) (((pri) << (8 - DT_NUM_IRQ_PRIO_BITS)) & 0xff) +/* + * In architecture variants with non-programmable fault exceptions + * (e.g. Cortex-M Baseline variants), hardware ensures processor faults + * are given the highest interrupt priority level. SVCalls are assigned + * the highest configurable priority level (level 0); note, however, that + * this interrupt level may be shared with HW interrupts. + * + * In Cortex variants with programmable fault exception priorities we + * assign the highest interrupt priority level (level 0) to processor faults + * with configurable priority. + * The highest priority level may be shared with either Zero-Latency IRQs (if + * support for the feature is enabled) or with SVCall priority level. + * Regular HW IRQs are always assigned priority levels lower than the priority + * levels for SVCalls, Zero-Latency IRQs and processor faults. + * + */ #if defined(CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS) #define _EXCEPTION_RESERVED_PRIO 1 #else