diff --git a/drivers/flash/flash_npcx_fiu_qspi.c b/drivers/flash/flash_npcx_fiu_qspi.c
index e8c557b8e25..3af0d4092a6 100644
--- a/drivers/flash/flash_npcx_fiu_qspi.c
+++ b/drivers/flash/flash_npcx_fiu_qspi.c
@@ -275,11 +275,6 @@ static int qspi_npcx_fiu_init(const struct device *dev)
 		}
 	}
 
-	/* Make sure there is no address field (UMA_ADDR_SIZE is zero) in UMA mode */
-	if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX4)) {
-		SET_FIELD(inst->UMA_ECTS, NPCX_UMA_ECTS_UMA_ADDR_SIZE, 0);
-	}
-
 	return 0;
 }
 
diff --git a/soc/arm/nuvoton_npcx/common/scfg.c b/soc/arm/nuvoton_npcx/common/scfg.c
index 42add909aa7..af5343e7e1a 100644
--- a/soc/arm/nuvoton_npcx/common/scfg.c
+++ b/soc/arm/nuvoton_npcx/common/scfg.c
@@ -145,16 +145,6 @@ void npcx_dbg_freeze_enable(bool enable)
 /* Pin-control driver registration */
 static int npcx_scfg_init(void)
 {
-	struct scfg_reg *inst_scfg = HAL_SFCG_INST();
-
-	/*
-	 * Set bit 7 of DEVCNT again for npcx7 series. Please see Errata
-	 * for more information. It will be fixed in next chip.
-	 */
-	if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
-		inst_scfg->DEVCNT |= BIT(7);
-	}
-
 	/* Change all pads whose default functionality isn't IO to GPIO */
 	for (int i = 0; i < ARRAY_SIZE(def_alts); i++) {
 		npcx_pinctrl_alt_sel(&def_alts[i], 0);
diff --git a/soc/arm/nuvoton_npcx/npcx4/soc.c b/soc/arm/nuvoton_npcx/npcx4/soc.c
index 29c0976adfa..28b868bda65 100644
--- a/soc/arm/nuvoton_npcx/npcx4/soc.c
+++ b/soc/arm/nuvoton_npcx/npcx4/soc.c
@@ -12,10 +12,25 @@
 
 LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 
-static int soc_init(void)
+#define NPCX_FIU_INST_INIT(node_id) DT_REG_ADDR(node_id),
+
+static uintptr_t fiu_insts[] = {
+	DT_FOREACH_STATUS_OKAY(nuvoton_npcx_fiu_qspi, NPCX_FIU_INST_INIT)
+};
+
+static int soc_npcx4_init(void)
 {
+	/*
+	 * Make sure UMA_ADDR_SIZE field of UMA_ECTS register is zero in npcx4
+	 * series. There should be no address field in UMA mode by default.
+	 */
+	for (int i = 0; i < ARRAY_SIZE(fiu_insts); i++) {
+		struct fiu_reg *const inst = (struct fiu_reg *)(fiu_insts[i]);
+
+		SET_FIELD(inst->UMA_ECTS, NPCX_UMA_ECTS_UMA_ADDR_SIZE, 0);
+	}
 
 	return 0;
 }
 
-SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+SYS_INIT(soc_npcx4_init, PRE_KERNEL_1, 0);
diff --git a/soc/arm/nuvoton_npcx/npcx7/soc.c b/soc/arm/nuvoton_npcx/npcx7/soc.c
index 31c867e1a8d..ae892a7d166 100644
--- a/soc/arm/nuvoton_npcx/npcx7/soc.c
+++ b/soc/arm/nuvoton_npcx/npcx7/soc.c
@@ -12,10 +12,18 @@
 
 LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 
-static int soc_init(void)
+static int soc_npcx7_init(void)
 {
+	struct scfg_reg *inst_scfg = (struct scfg_reg *)
+			DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg);
+
+	/*
+	 * Set bit 7 of DEVCNT again for npcx7 series. Please see Errata
+	 * for more information. It will be fixed in next chip.
+	 */
+	inst_scfg->DEVCNT |= BIT(7);
 
 	return 0;
 }
 
-SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+SYS_INIT(soc_npcx7_init, PRE_KERNEL_1, 0);
diff --git a/soc/arm/nuvoton_npcx/npcx9/CMakeLists.txt b/soc/arm/nuvoton_npcx/npcx9/CMakeLists.txt
index ee55c1c2a5b..5b2aad82a5a 100644
--- a/soc/arm/nuvoton_npcx/npcx9/CMakeLists.txt
+++ b/soc/arm/nuvoton_npcx/npcx9/CMakeLists.txt
@@ -1,7 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(${ZEPHYR_BASE}/drivers)
-
-zephyr_sources(
-  soc.c
-)
diff --git a/soc/arm/nuvoton_npcx/npcx9/soc.c b/soc/arm/nuvoton_npcx/npcx9/soc.c
deleted file mode 100644
index 6a11cce38bc..00000000000
--- a/soc/arm/nuvoton_npcx/npcx9/soc.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (c) 2021 Nuvoton Technology Corporation.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/kernel.h>
-#include <zephyr/device.h>
-#include <zephyr/init.h>
-#include <soc.h>
-#include <zephyr/logging/log.h>
-
-LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
-
-static int soc_init(void)
-{
-
-	return 0;
-}
-
-SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);