soc: espressif: esp32c3: simple boot support
Add simplistic booting method which allows to run applications without the 2nd stage bootloader. - introduce memory layout header file - update and optimize default and mcuboot linker scripts - remove building multiple binaries during the application build Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit is contained in:
Marek Matej
Anas Nashif
parent
43e3088c2d
commit
f9008b5330
5 changed files with 865 additions and 577 deletions
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@ -13,6 +13,33 @@ zephyr_include_directories(.)
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zephyr_library_sources_ifdef(CONFIG_PM power.c)
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zephyr_library_sources_ifdef(CONFIG_PM power.c)
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zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
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zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
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# get flash size to use in esptool as string
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math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
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if(NOT CONFIG_BOOTLOADER_MCUBOOT)
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if(CONFIG_BUILD_OUTPUT_BIN)
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# make ESP ROM loader compatible image
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message("ESP-IDF path: ${ESP_IDF_PATH}")
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set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py)
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message("esptool path: ${ESPTOOL_PY}")
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set(ELF2IMAGE_ARG "")
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if(NOT CONFIG_MCUBOOT)
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set(ELF2IMAGE_ARG "--ram-only-header")
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endif()
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set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
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COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY}
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ARGS --chip esp32c3 elf2image ${ELF2IMAGE_ARG}
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--flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB
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-o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
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${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
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endif()
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endif()
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# get code-partition slot0 address
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# get code-partition slot0 address
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dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
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dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
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dt_reg_addr(img_0_off PATH ${dts_partition_path})
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dt_reg_addr(img_0_off PATH ${dts_partition_path})
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@ -21,51 +48,25 @@ dt_reg_addr(img_0_off PATH ${dts_partition_path})
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dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
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dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
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dt_reg_addr(boot_off PATH ${dts_partition_path})
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dt_reg_addr(boot_off PATH ${dts_partition_path})
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# get flash size to use in esptool as string
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if(CONFIG_ESP_SIMPLE_BOOT)
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math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
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board_finalize_runner_args(esp32 "--esp-app-address=${boot_off}")
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else()
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if(CONFIG_BOOTLOADER_ESP_IDF)
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board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
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set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}")
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if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin")
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file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR})
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file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin")
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endif()
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if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin")
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file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR})
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file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin")
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endif()
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board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin")
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board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin")
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board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000")
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endif()
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endif()
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if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF)
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if(CONFIG_MCUBOOT)
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# search from cross references between bootloader sections
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if(CONFIG_BUILD_OUTPUT_BIN)
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message("check_callgraph using: ${ESP_IDF_PATH}/tools/ci/check_callgraph.py")
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set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
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set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
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COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py
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COMMAND
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ARGS --chip esp32c3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB
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${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/ci/check_callgraph.py
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-o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
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ARGS
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${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
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--rtl-dirs ${CMAKE_BINARY_DIR}/zephyr
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endif()
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--elf-file ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf
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find-refs --from-section=.iram0.iram_loader --to-section=.iram0.text
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if(CONFIG_MCUBOOT)
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--exit-code)
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board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin")
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endif()
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endif()
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endif()
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board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}")
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board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
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if(CONFIG_MCUBOOT)
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if(CONFIG_MCUBOOT)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
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else()
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else()
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File diff suppressed because it is too large
Load diff
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@ -1,20 +1,15 @@
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/*
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/*
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* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
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* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* Linker script for the esp32c3 platform.
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/linker/linker-tool.h>
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#include <zephyr/linker/linker-tool.h>
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#include "memory.h"
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#ifdef CONFIG_XIP
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#ifdef CONFIG_XIP
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#error "ESP32C3 bootloader cannot use XIP"
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#error "ESP32C3 bootloader cannot use XIP"
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#endif /* CONFIG_XIP */
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#endif /* CONFIG_XIP */
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@ -25,19 +20,17 @@
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#define RAMABLE_REGION dram_seg
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#define RAMABLE_REGION dram_seg
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#define RODATA_REGION dram_seg
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#define RODATA_REGION dram_seg
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#define IRAM_REGION iram_seg
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#define IRAM_LOADER_REGION iram_loader_seg
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#define ROMABLE_REGION dram_seg
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#define ROMABLE_REGION dram_seg
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#define IROM_SEG_ALIGN 0x4
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/* Global symbols required for espressif hal build */
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/* Global symbols required for espressif hal build */
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MEMORY
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MEMORY
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{
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{
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iram_seg (RX) : org = 0x403CA000, len = 0x9000
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iram_seg (RX) : org = BOOTLOADER_IRAM_SEG_START,
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iram_loader_seg (RX) : org = 0x403D3000, len = 0x4000
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len = BOOTLOADER_IRAM_SEG_LEN
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dram_seg (RW) : org = 0x3FCD8000, len = 0x9000
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iram_loader_seg (RX) : org = BOOTLOADER_IRAM_LOADER_SEG_START,
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len = BOOTLOADER_IRAM_LOADER_SEG_LEN
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dram_seg (RW) : org = BOOTLOADER_DRAM_SEG_START,
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len = BOOTLOADER_DRAM_SEG_LEN
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#ifdef CONFIG_GEN_ISR_TABLES
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
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IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
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@ -49,15 +42,135 @@ ENTRY(CONFIG_KERNEL_ENTRY)
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SECTIONS
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SECTIONS
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{
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{
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
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.iram0.loader_text :
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{
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{
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_rodata_start = ABSOLUTE(.);
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. = ALIGN (16);
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_loader_text_start = ABSOLUTE(.);
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*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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/* TODO: cross-segments calls in the libzephyr.a:device.* */
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*libapp.a:flash_map_extended.*(.literal .text .literal.* .text.*)
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*libzephyr.a:cbprintf_nano.*(.literal .text .literal.* .text.*)
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*libzephyr.a:cpu.*(.literal .text .literal.* .text.*)
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*libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
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*libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*)
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*libzephyr.a:flash_map.*(.literal .text .literal.* .text.*)
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*libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*)
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*libzephyr.a:heap.*(.literal .text .literal.* .text.*)
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*libkernel.a:kheap.*(.literal .text .literal.* .text.*)
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*libkernel.a:mempool.*(.literal .text .literal.* .text.*)
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*(.literal.bootloader_mmap .text.bootloader_mmap)
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*(.literal.bootloader_munmap .text.bootloader_munmap)
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*libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*)
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*libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
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*(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*)
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*(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler)
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*(.literal.esp_log_timestamp .text.esp_log_timestamp)
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*(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp)
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*(.literal.esp_system_abort .text.esp_system_abort)
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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_loader_text_end = ABSOLUTE(.);
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_iram_end = ABSOLUTE(.);
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} > iram_loader_seg
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.iram0.text :
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{
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/* Vectors go to IRAM */
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_iram_start = ABSOLUTE(.);
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_init_start = ABSOLUTE(.);
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KEEP(*(.exception_vectors.text));
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. = ALIGN(256);
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_invalid_pc_placeholder = ABSOLUTE(.);
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_iram_text_start = ABSOLUTE(.);
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KEEP(*(.exception.entry*)); /* contains _isr_wrapper */
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*(.exception.other*)
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. = ALIGN(4);
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*(.entry.text)
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*(.init.literal)
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*(.init)
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. = ALIGN(4);
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*(.iram1 .iram1.*)
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*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
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/* C3 memprot requires 512 B alignment for split lines */
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. = ALIGN (16);
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_init_end = ABSOLUTE(.);
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. = ALIGN(16);
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*(.iram.data)
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*(.iram.data*)
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. = ALIGN(16);
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*(.iram.bss)
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*(.iram.bss*)
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. = ALIGN(16);
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*(.literal .text .literal.* .text.*)
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*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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/* CPU will try to prefetch up to 16 bytes of
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* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
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* safe access to up to 16 bytes after the last real instruction, add
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* dummy bytes to ensure this
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*/
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. += 16;
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_text_end = ABSOLUTE(.);
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_etext = .;
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/* Similar to _iram_start, this symbol goes here so it is
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* resolved by addr2line in preference to the first symbol in
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* the flash.text segment.
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*/
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_flash_cache_start = ABSOLUTE(0);
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} > iram_seg
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.dram0.data :
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{
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. = ALIGN(4);
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__data_start = ABSOLUTE(.);
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d.*)
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*(.data1)
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#ifdef CONFIG_RISCV_GP
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__global_pointer$ = . + 0x800;
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#endif /* CONFIG_RISCV_GP */
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.sdata2)
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*(.sdata2.*)
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*(.gnu.linkonce.s2.*)
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*libzephyr.a:mmu_hal.*(.rodata .rodata.*)
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*libzephyr.a:rtc_clk.*(.rodata .rodata.*)
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KEEP(*(.jcr))
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*(.dram1 .dram1.*)
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. = ALIGN(4);
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#include <snippets-rwdata.ld>
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. = ALIGN(4);
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*(.rodata_desc .rodata_desc.*)
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*(.rodata_desc .rodata_desc.*)
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*(.rodata_custom_desc .rodata_custom_desc.*)
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*(.rodata_custom_desc .rodata_custom_desc.*)
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__rodata_region_start = .;
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. = ALIGN(4);
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. = ALIGN(4);
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#include <snippets-rodata.ld>
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#include <snippets-rodata.ld>
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. = ALIGN(4);
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. = ALIGN(4);
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@ -108,39 +221,14 @@ SECTIONS
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_thread_local_end = ABSOLUTE(.);
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_thread_local_end = ABSOLUTE(.);
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/* _rodata_reserved_end = ABSOLUTE(.); */
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/* _rodata_reserved_end = ABSOLUTE(.); */
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. = ALIGN(4);
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. = ALIGN(4);
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} GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
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} > dram_seg
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#include <zephyr/linker/common-rom/common-rom-cpp.ld>
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#include <zephyr/linker/common-rom/common-rom-cpp.ld>
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#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
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#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
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#include <zephyr/linker/common-rom/common-rom-debug.ld>
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#include <zephyr/linker/common-rom/common-rom-debug.ld>
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#include <zephyr/linker/common-rom/common-rom-misc.ld>
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#include <zephyr/linker/common-rom/common-rom-misc.ld>
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#include <snippets-sections.ld>
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#include <snippets-sections.ld>
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.dram0.data :
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{
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. = ALIGN(4);
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__data_start = ABSOLUTE(.);
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d.*)
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*(.data1)
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#ifdef CONFIG_RISCV_GP
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__global_pointer$ = . + 0x800;
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#endif /* CONFIG_RISCV_GP */
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.sdata2)
|
|
||||||
*(.sdata2.*)
|
|
||||||
*(.gnu.linkonce.s2.*)
|
|
||||||
*libzephyr.a:mmu_hal.*(.rodata .rodata.*)
|
|
||||||
*libzephyr.a:rtc_clk.*(.rodata .rodata.*)
|
|
||||||
KEEP(*(.jcr))
|
|
||||||
*(.dram1 .dram1.*)
|
|
||||||
. = ALIGN(4);
|
|
||||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
|
||||||
|
|
||||||
#include <zephyr/linker/cplusplus-rom.ld>
|
#include <zephyr/linker/cplusplus-rom.ld>
|
||||||
#include <zephyr/linker/thread-local-storage.ld>
|
#include <zephyr/linker/thread-local-storage.ld>
|
||||||
#include <snippets-data-sections.ld>
|
#include <snippets-data-sections.ld>
|
||||||
|
|
@ -150,17 +238,16 @@ SECTIONS
|
||||||
|
|
||||||
#include <zephyr/linker/common-rom/common-rom-logging.ld>
|
#include <zephyr/linker/common-rom/common-rom-logging.ld>
|
||||||
|
|
||||||
.dram0.end :
|
.noinit (NOLOAD):
|
||||||
{
|
{
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
#include <snippets-rwdata.ld>
|
*(.noinit)
|
||||||
|
*(.noinit.*)
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
_end = ABSOLUTE(.);
|
} > dram_seg
|
||||||
__data_end = ABSOLUTE(.);
|
|
||||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
|
||||||
|
|
||||||
/* Shared RAM */
|
/* Shared RAM */
|
||||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
.bss (NOLOAD):
|
||||||
{
|
{
|
||||||
. = ALIGN (8);
|
. = ALIGN (8);
|
||||||
_bss_start = ABSOLUTE(.);
|
_bss_start = ABSOLUTE(.);
|
||||||
|
|
@ -182,155 +269,13 @@ SECTIONS
|
||||||
. = ALIGN (8);
|
. = ALIGN (8);
|
||||||
__bss_end = ABSOLUTE(.);
|
__bss_end = ABSOLUTE(.);
|
||||||
_bss_end = ABSOLUTE(.);
|
_bss_end = ABSOLUTE(.);
|
||||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
} > dram_seg
|
||||||
|
|
||||||
SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
*(.noinit)
|
|
||||||
*(.noinit.*)
|
|
||||||
. = ALIGN(4);
|
|
||||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
|
||||||
|
|
||||||
.iram_loader.text :
|
|
||||||
{
|
|
||||||
. = ALIGN (16);
|
|
||||||
_loader_text_start = ABSOLUTE(.);
|
|
||||||
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
|
||||||
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
|
|
||||||
*libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:bootloader_flash_config_esp32c3.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:bootloader_init_common.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
|
|
||||||
*libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
|
|
||||||
*libzephyr.a:bootloader_efuse_esp32c3.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*)
|
|
||||||
*esp_mcuboot.*(.literal .text .literal.* .text.*)
|
|
||||||
*esp_loader.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
|
|
||||||
*libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*)
|
|
||||||
*libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*)
|
|
||||||
*libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*)
|
|
||||||
*(.fini.literal)
|
|
||||||
*(.fini)
|
|
||||||
*(.gnu.version)
|
|
||||||
_loader_text_end = ABSOLUTE(.);
|
|
||||||
} > iram_loader_seg
|
|
||||||
|
|
||||||
/* .iram0.text : ALIGN(4) */
|
|
||||||
SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))
|
|
||||||
{
|
|
||||||
/* Vectors go to IRAM */
|
|
||||||
_iram_start = ABSOLUTE(.);
|
|
||||||
_init_start = ABSOLUTE(.);
|
|
||||||
|
|
||||||
KEEP(*(.exception_vectors.text));
|
|
||||||
. = ALIGN(256);
|
|
||||||
|
|
||||||
_invalid_pc_placeholder = ABSOLUTE(.);
|
|
||||||
|
|
||||||
_iram_text_start = ABSOLUTE(.);
|
|
||||||
|
|
||||||
KEEP(*(.exception.entry*)); /* contains _isr_wrapper */
|
|
||||||
*(.exception.other*)
|
|
||||||
. = ALIGN(4);
|
|
||||||
|
|
||||||
*(.entry.text)
|
|
||||||
*(.init.literal)
|
|
||||||
*(.init)
|
|
||||||
. = ALIGN(4);
|
|
||||||
*(.iram1 .iram1.*)
|
|
||||||
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
_init_end = ABSOLUTE(.);
|
|
||||||
} GROUP_DATA_LINK_IN(IRAM_LOADER_REGION, ROMABLE_REGION)
|
|
||||||
|
|
||||||
.iram0.text_end (NOLOAD) :
|
|
||||||
{
|
|
||||||
/* C3 memprot requires 512 B alignment for split lines */
|
|
||||||
. = ALIGN (16);
|
|
||||||
} GROUP_LINK_IN(IRAM_LOADER_REGION)
|
|
||||||
|
|
||||||
.iram0.data :
|
|
||||||
{
|
|
||||||
. = ALIGN(16);
|
|
||||||
*(.iram.data)
|
|
||||||
*(.iram.data*)
|
|
||||||
} GROUP_DATA_LINK_IN(IRAM_LOADER_REGION, ROMABLE_REGION)
|
|
||||||
|
|
||||||
.iram0.bss (NOLOAD) :
|
|
||||||
{
|
|
||||||
. = ALIGN(16);
|
|
||||||
*(.iram.bss)
|
|
||||||
*(.iram.bss*)
|
|
||||||
|
|
||||||
. = ALIGN(16);
|
|
||||||
_iram_end = ABSOLUTE(.);
|
|
||||||
} GROUP_LINK_IN(IRAM_LOADER_REGION)
|
|
||||||
|
|
||||||
.flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN)
|
|
||||||
{
|
|
||||||
. = SIZEOF(_RODATA_SECTION_NAME);
|
|
||||||
. = ALIGN(4) + 0x20;
|
|
||||||
_rodata_reserved_start = .;
|
|
||||||
} GROUP_LINK_IN(IRAM_REGION)
|
|
||||||
|
|
||||||
.flash.text : ALIGN(IROM_SEG_ALIGN)
|
|
||||||
{
|
|
||||||
_stext = .;
|
|
||||||
_text_start = ABSOLUTE(.);
|
|
||||||
|
|
||||||
*(.literal .text .literal.* .text.*)
|
|
||||||
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
|
||||||
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
|
|
||||||
*(.fini.literal)
|
|
||||||
*(.fini)
|
|
||||||
*(.gnu.version)
|
|
||||||
|
|
||||||
/* CPU will try to prefetch up to 16 bytes of
|
|
||||||
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
|
|
||||||
* safe access to up to 16 bytes after the last real instruction, add
|
|
||||||
* dummy bytes to ensure this
|
|
||||||
*/
|
|
||||||
. += 16;
|
|
||||||
|
|
||||||
_text_end = ABSOLUTE(.);
|
|
||||||
_etext = .;
|
|
||||||
|
|
||||||
/* Similar to _iram_start, this symbol goes here so it is
|
|
||||||
* resolved by addr2line in preference to the first symbol in
|
|
||||||
* the flash.text segment.
|
|
||||||
*/
|
|
||||||
_flash_cache_start = ABSOLUTE(0);
|
|
||||||
} GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
|
|
||||||
|
|
||||||
/* linker rel sections*/
|
/* linker rel sections*/
|
||||||
#include <zephyr/linker/rel-sections.ld>
|
#include <zephyr/linker/rel-sections.ld>
|
||||||
|
|
||||||
#ifdef CONFIG_GEN_ISR_TABLES
|
#ifdef CONFIG_GEN_ISR_TABLES
|
||||||
#include <zephyr/linker/intlist.ld>
|
#include <zephyr/linker/intlist.ld>
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include <zephyr/linker/debug-sections.ld>
|
#include <zephyr/linker/debug-sections.ld>
|
||||||
|
|
|
||||||
67
soc/espressif/esp32c3/memory.h
Normal file
67
soc/espressif/esp32c3/memory.h
Normal file
|
|
@ -0,0 +1,67 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
#pragma once
|
||||||
|
|
||||||
|
/* SRAM0 (16kB) memory */
|
||||||
|
#define SRAM0_IRAM_START 0x4037c000
|
||||||
|
#define SRAM0_SIZE 0x4000
|
||||||
|
/* SRAM1 (384kB) memory */
|
||||||
|
#define SRAM1_DRAM_START 0x3fc80000
|
||||||
|
#define SRAM1_IRAM_START 0x40380000
|
||||||
|
/* ICache size is fixed to 16KB on ESP32-C3 */
|
||||||
|
#define ICACHE_SIZE SRAM0_SIZE
|
||||||
|
|
||||||
|
/** Simplified memory map for the bootloader.
|
||||||
|
* Make sure the bootloader can load into main memory without overwriting itself.
|
||||||
|
*
|
||||||
|
* ESP32-C3 ROM static data usage is as follows:
|
||||||
|
* - 0x3fccae00 - 0x3fcdc710: Shared buffers, used in UART/USB/SPI download mode only
|
||||||
|
* - 0x3fcdc710 - 0x3fcde710: PRO CPU stack, can be reclaimed as heap after RTOS startup
|
||||||
|
* - 0x3fcde710 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)
|
||||||
|
*
|
||||||
|
* The 2nd stage bootloader can take space up to the end of ROM shared
|
||||||
|
* buffers area (0x3fcdc710).
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* The offset between Dbus and Ibus.
|
||||||
|
* Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses.
|
||||||
|
*/
|
||||||
|
#define IRAM_DRAM_OFFSET 0x700000
|
||||||
|
#define DRAM_BUFFERS_START 0x3fccae00
|
||||||
|
#define DRAM_STACK_START 0x3fcdc710
|
||||||
|
#define DRAM_ROM_BSS_DATA_START 0x3fcde710
|
||||||
|
|
||||||
|
/* Base address used for calculating memory layout
|
||||||
|
* counted from Dbus backwards and back to the Ibus
|
||||||
|
*/
|
||||||
|
#define BOOTLOADER_USABLE_DRAM_END DRAM_BUFFERS_START
|
||||||
|
|
||||||
|
/* For safety margin between bootloader data section and startup stacks */
|
||||||
|
#define BOOTLOADER_STACK_OVERHEAD 0x0
|
||||||
|
/* These lengths can be adjusted, if necessary: */
|
||||||
|
#define BOOTLOADER_DRAM_SEG_LEN 0x9000
|
||||||
|
#define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x3000
|
||||||
|
#define BOOTLOADER_IRAM_SEG_LEN 0x8000
|
||||||
|
|
||||||
|
/* Start of the lower region is determined by region size and the end of the higher region */
|
||||||
|
#define BOOTLOADER_DRAM_SEG_END (BOOTLOADER_USABLE_DRAM_END + BOOTLOADER_STACK_OVERHEAD)
|
||||||
|
#define BOOTLOADER_DRAM_SEG_START (BOOTLOADER_DRAM_SEG_END - BOOTLOADER_DRAM_SEG_LEN)
|
||||||
|
#define BOOTLOADER_IRAM_LOADER_SEG_START (BOOTLOADER_DRAM_SEG_START - \
|
||||||
|
BOOTLOADER_IRAM_LOADER_SEG_LEN + IRAM_DRAM_OFFSET)
|
||||||
|
#define BOOTLOADER_IRAM_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN)
|
||||||
|
|
||||||
|
/* Flash */
|
||||||
|
#ifdef CONFIG_FLASH_SIZE
|
||||||
|
#define FLASH_SIZE CONFIG_FLASH_SIZE
|
||||||
|
#else
|
||||||
|
#define FLASH_SIZE 0x400000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Cached memory */
|
||||||
|
#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE
|
||||||
|
#define IROM_SEG_ORG 0x42000000
|
||||||
|
#define IROM_SEG_LEN FLASH_SIZE
|
||||||
|
#define DROM_SEG_ORG 0x3c000000
|
||||||
|
#define DROM_SEG_LEN FLASH_SIZE
|
||||||
|
|
@ -43,17 +43,6 @@ extern void esp_reset_reason_init(void);
|
||||||
*/
|
*/
|
||||||
void __attribute__((section(".iram1"))) __esp_platform_start(void)
|
void __attribute__((section(".iram1"))) __esp_platform_start(void)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_RISCV_GP
|
|
||||||
/* Configure the global pointer register
|
|
||||||
* (This should be the first thing startup does, as any other piece of code could be
|
|
||||||
* relaxed by the linker to access something relative to __global_pointer$)
|
|
||||||
*/
|
|
||||||
__asm__ __volatile__(".option push\n"
|
|
||||||
".option norelax\n"
|
|
||||||
"la gp, __global_pointer$\n"
|
|
||||||
".option pop");
|
|
||||||
#endif /* CONFIG_RISCV_GP */
|
|
||||||
|
|
||||||
__asm__ __volatile__("la t0, _esp32c3_vector_table\n"
|
__asm__ __volatile__("la t0, _esp32c3_vector_table\n"
|
||||||
"csrw mtvec, t0\n");
|
"csrw mtvec, t0\n");
|
||||||
|
|
||||||
|
|
@ -64,12 +53,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void)
|
||||||
|
|
||||||
esp_reset_reason_init();
|
esp_reset_reason_init();
|
||||||
|
|
||||||
#ifdef CONFIG_MCUBOOT
|
#ifndef CONFIG_MCUBOOT
|
||||||
/* MCUboot early initialisation.
|
|
||||||
*/
|
|
||||||
bootloader_init();
|
|
||||||
|
|
||||||
#else
|
|
||||||
/* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
|
/* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
|
||||||
* related issues in application. Hence disable that as we are about to start
|
* related issues in application. Hence disable that as we are about to start
|
||||||
* Zephyr environment.
|
* Zephyr environment.
|
||||||
|
|
@ -106,8 +90,8 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void)
|
||||||
/**
|
/**
|
||||||
* This function initialise the Flash chip to the user-defined settings.
|
* This function initialise the Flash chip to the user-defined settings.
|
||||||
*
|
*
|
||||||
* In bootloader, we only init Flash (and MSPI) to a preliminary state, for being flexible to
|
* In bootloader, we only init Flash (and MSPI) to a preliminary
|
||||||
* different chips.
|
* state, for being flexible to different chips.
|
||||||
* In this stage, we re-configure the Flash (and MSPI) to required configuration
|
* In this stage, we re-configure the Flash (and MSPI) to required configuration
|
||||||
*/
|
*/
|
||||||
spi_flash_init_chip_state();
|
spi_flash_init_chip_state();
|
||||||
|
|
@ -127,7 +111,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void)
|
||||||
spi_flash_guard_set(&g_flash_guard_default_ops);
|
spi_flash_guard_set(&g_flash_guard_default_ops);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* CONFIG_MCUBOOT */
|
#endif /* !CONFIG_MCUBOOT */
|
||||||
|
|
||||||
/*Initialize the esp32c3 interrupt controller */
|
/*Initialize the esp32c3 interrupt controller */
|
||||||
esp_intr_initialize();
|
esp_intr_initialize();
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue