diff --git a/soc/espressif/esp32c3/CMakeLists.txt b/soc/espressif/esp32c3/CMakeLists.txt index a5c44685ef1..75ee06e2a06 100644 --- a/soc/espressif/esp32c3/CMakeLists.txt +++ b/soc/espressif/esp32c3/CMakeLists.txt @@ -13,6 +13,33 @@ zephyr_include_directories(.) zephyr_library_sources_ifdef(CONFIG_PM power.c) zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) +# get flash size to use in esptool as string +math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") + +if(NOT CONFIG_BOOTLOADER_MCUBOOT) + + if(CONFIG_BUILD_OUTPUT_BIN) + # make ESP ROM loader compatible image + message("ESP-IDF path: ${ESP_IDF_PATH}") + + set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py) + message("esptool path: ${ESPTOOL_PY}") + + set(ELF2IMAGE_ARG "") + if(NOT CONFIG_MCUBOOT) + set(ELF2IMAGE_ARG "--ram-only-header") + endif() + + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY} + ARGS --chip esp32c3 elf2image ${ELF2IMAGE_ARG} + --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB + -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) + endif() + +endif() + # get code-partition slot0 address dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") dt_reg_addr(img_0_off PATH ${dts_partition_path}) @@ -21,51 +48,25 @@ dt_reg_addr(img_0_off PATH ${dts_partition_path}) dt_nodelabel(dts_partition_path NODELABEL "boot_partition") dt_reg_addr(boot_off PATH ${dts_partition_path}) -# get flash size to use in esptool as string -math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") - -if(CONFIG_BOOTLOADER_ESP_IDF) - - set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}") - - if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin") - file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) - file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin") - endif() - - if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin") - file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) - file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin") - endif() - - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin") - - board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") - +if(CONFIG_ESP_SIMPLE_BOOT) + board_finalize_runner_args(esp32 "--esp-app-address=${boot_off}") +else() + board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") endif() -if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) - - if(CONFIG_BUILD_OUTPUT_BIN) +if(CONFIG_MCUBOOT) + # search from cross references between bootloader sections + message("check_callgraph using: ${ESP_IDF_PATH}/tools/ci/check_callgraph.py") set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py - ARGS --chip esp32c3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB - -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin - ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) - endif() - - if(CONFIG_MCUBOOT) - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") - endif() - + COMMAND + ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/ci/check_callgraph.py + ARGS + --rtl-dirs ${CMAKE_BINARY_DIR}/zephyr + --elf-file ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf + find-refs --from-section=.iram0.iram_loader --to-section=.iram0.text + --exit-code) endif() -board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") - -board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") - if(CONFIG_MCUBOOT) set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") else() diff --git a/soc/espressif/esp32c3/default.ld b/soc/espressif/esp32c3/default.ld index 39e6906c62f..120f66d852d 100644 --- a/soc/espressif/esp32c3/default.ld +++ b/soc/espressif/esp32c3/default.ld @@ -1,55 +1,42 @@ /* - * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. * SPDX-License-Identifier: Apache-2.0 */ -/** - * @file - * @brief Linker command/script file - * - * Linker script for the esp32c3 platform. - */ - #include #include #include #include -#define RAMABLE_REGION dram0_0_seg -#define RODATA_REGION drom0_0_seg -#define IRAM_REGION iram0_0_seg -#define FLASH_CODE_REGION irom0_0_seg +#include "memory.h" -#define ROMABLE_REGION ROM - -#define SRAM_IRAM_START 0x4037C000 -#define SRAM_DRAM_START 0x3FC7C000 -#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */ -#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) -/* SRAM_DRAM_END is equivalent 2nd stage bootloader iram_loader_seg - start address (that should not be overlapped) */ -#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET -#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE) -#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE) -#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG - -#ifdef CONFIG_FLASH_SIZE -#define FLASH_SIZE CONFIG_FLASH_SIZE +/* The "user_iram_end" represents the 2nd stage bootloader + * "iram_loader_seg" start address (that should not be overlapped). + * If no bootloader is used, we can extend it to gain more user ram. + */ +#ifdef CONFIG_ESP_SIMPLE_BOOT +user_iram_end = (DRAM_BUFFERS_START + IRAM_DRAM_OFFSET); #else -#define FLASH_SIZE 0x400000 +user_iram_end = BOOTLOADER_IRAM_LOADER_SEG_START; #endif -#ifdef CONFIG_BOOTLOADER_ESP_IDF -#define IROM_SEG_ORG 0x42000020 -#define IROM_SEG_LEN (FLASH_SIZE-0x20) -#define IROM_SEG_ALIGN 0x4 -#else -#define IROM_SEG_ORG 0x42000000 -#define IROM_SEG_LEN FLASH_SIZE -#define IROM_SEG_ALIGN 0x10000 -#endif +/* User available SRAM memory segments */ +user_iram_seg_org = SRAM1_IRAM_START; +user_dram_seg_org = SRAM1_DRAM_START; +user_dram_end = (user_iram_end - IRAM_DRAM_OFFSET); +user_idram_size = (user_dram_end - user_dram_seg_org); +user_iram_seg_len = user_idram_size; +user_dram_seg_len = user_idram_size; -/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. +/* Aliases */ +#define FLASH_CODE_REGION irom0_0_seg +#define RODATA_REGION drom0_0_seg +#define IRAM_REGION iram0_0_seg +#define DRAM_REGION dram0_0_seg +#define RAMABLE_REGION dram0_0_seg +#define ROMABLE_REGION FLASH + +/* Flash segments (rodata and text) should be mapped in the virtual address spaces. * Executing directly from LMA is not possible. */ #undef GROUP_ROM_LINK_IN #define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion @@ -57,15 +44,21 @@ /* Global symbols required for espressif hal build */ MEMORY { - mcuboot_hdr (RX): org = 0x0, len = 0x20 - metadata (RX): org = 0x20, len = 0x20 - ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40 +#ifdef CONFIG_BOOTLOADER_MCUBOOT + mcuboot_hdr (R): org = 0x0, len = 0x20 + metadata (R): org = 0x20, len = 0x20 + FLASH (R): org = 0x40, len = FLASH_SIZE - 0x40 +#else + /* Make safety margin in the FLASH memory size so the + * (esp_img_header + (n*esp_seg_headers)) would fit */ + FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100 +#endif + + iram0_0_seg(RX): org = user_iram_seg_org, len = user_iram_seg_len + dram0_0_seg(RW): org = user_dram_seg_org, len = user_dram_seg_len - iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN - - drom0_0_seg (R) : org = 0x3C000040, len = FLASH_SIZE - 0x40 - dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE + drom0_0_seg (R): org = DROM_SEG_ORG, len = DROM_SEG_LEN rtc_iram_seg(RWX): org = 0x50000000, len = 0x2000 @@ -74,7 +67,6 @@ MEMORY #endif } - /* The line below defines location alias for .rtc.data section * As C3 only has RTC fast memory, this is not configurable like * on other targets. @@ -86,8 +78,11 @@ ENTRY(CONFIG_KERNEL_ENTRY) _rom_store_table = 0; +_iram_dram_offset = IRAM_DRAM_OFFSET; + SECTIONS { +#ifdef CONFIG_BOOTLOADER_MCUBOOT /* Reserve space for MCUboot header in the binary */ .mcuboot_header : { @@ -98,37 +93,564 @@ SECTIONS } > mcuboot_hdr .metadata : { - /* Magic byte for load header */ + /* 0. Magic byte for load header */ LONG(0xace637d3) - /* Application entry point address */ + /* 1. Application entry point address */ KEEP(*(.entry_addr)) /* IRAM metadata: - * - Destination address (VMA) for IRAM region - * - Flash offset (LMA) for start of IRAM region - * - Size of IRAM region + * 2. Destination address (VMA) for IRAM region + * 3. Flash offset (LMA) for start of IRAM region + * 4. Size of IRAM region */ LONG(ADDR(.iram0.text)) LONG(LOADADDR(.iram0.text)) - LONG(SIZEOF(.iram0.text)) + LONG(LOADADDR(.iram0.data) - LOADADDR(.iram0.text)) /* DRAM metadata: - * - Destination address (VMA) for DRAM region - * - Flash offset (LMA) for start of DRAM region - * - Size of DRAM region + * 5. Destination address (VMA) for DRAM region + * 6. Flash offset (LMA) for start of DRAM region + * 7. Size of DRAM region */ LONG(ADDR(.dram0.data)) LONG(LOADADDR(.dram0.data)) - LONG(LOADADDR(.dummy.dram.data) + SIZEOF(.dummy.dram.data) - LOADADDR(.dram0.data)) + LONG(LOADADDR(.dram0.end) - LOADADDR(.dram0.data)) } > metadata +#endif /* CONFIG_BOOTLOADER_MCUBOOT */ -#include - _image_drom_start = LOADADDR(_RODATA_SECTION_NAME); - _image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start; - _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME); + iram_vma = ADDR(.iram0.text); + iram_lma = LOADADDR(.iram0.text); + iram_size_field = LOADADDR(.iram0.data) - LOADADDR(.iram0.text); - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) + dram_vma = ADDR(.dram0.data); + dram_lma = LOADADDR(.dram0.data); + dram_size_field = LOADADDR(.dram0.end) - LOADADDR(.dram0.data); + + #include + + /* --- START OF RTC --- */ + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + *rtc_wake_stub*.o(.literal .text .literal.* .text.*) + } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) + + /* This section is required to skip rtc.text area because the text and + * data segments reflect the same address space on different buses. + */ + .rtc.dummy (NOLOAD): + { + . = SIZEOF(.rtc.text); + } GROUP_LINK_IN(rtc_iram_seg) + + .rtc.data : + { + _rtc_data_start = ABSOLUTE(.); + *(.rtc.data) + *(.rtc.rodata) + *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) + _rtc_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) + + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.o(.bss .bss.*) + *rtc_wake_stub*.o(COMMON) + _rtc_bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(rtc_iram_seg) + + /* This section located in RTC SLOW Memory area. + * It holds data marked with RTC_SLOW_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : + { + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4) ; + _rtc_force_slow_end = ABSOLUTE(.); + } > rtc_slow_seg + + /* Get size of rtc slow data */ + _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); + + /* --- END OF RTC --- */ + + /* --- START OF IRAM --- */ + + .iram0.text : ALIGN(4) + { + /* Vectors go to IRAM */ + _iram_start = ABSOLUTE(.); + _init_start = ABSOLUTE(.); + + KEEP(*(.exception_vectors.text)); + . = ALIGN(256); + + _invalid_pc_placeholder = ABSOLUTE(.); + + KEEP(*(.exception.entry*)); /* contains _isr_wrapper */ + *(.exception.other*) + . = ALIGN(4); + + *(.entry.text) + *(.init.literal) + *(.init) + . = ALIGN(4); + + _init_end = ABSOLUTE(.); + _iram_text_start = ABSOLUTE(.); + + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + *libzephyr.a:panic.*(.literal .text .literal.* .text.*) + *libzephyr.a:loader.*(.literal .text .literal.* .text.*) + *libarch__riscv__core.a:(.literal .text .literal.* .text.*) + *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*) + *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*) + *libsubsys__net__ip.a:(.literal .text .literal.* .text.*) + *libsubsys__net.a:(.literal .text .literal.* .text.*) + *libkernel.a:(.literal .text .literal.* .text.*) + *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) + *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:esp32c3_sys_timer.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) + *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) + *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) + *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) + *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:rtc_*.*(.literal .text .literal.* .text.*) + *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) + *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) + *liblib__libc__picolib.a:string.*(.literal .text .literal.* .text.*) + *libzephyr.a:periph_ctrl.*(.literal .text .literal.* .text.*) + *libgcov.a:(.literal .text .literal.* .text.*) + *libphy.a:( .phyiram .phyiram.*) + *libc.a:*(.literal .text .literal.* .text.*) + + /* [mapping:hal] */ + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:ledc_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:i2c_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.literal .literal.* .text .text.*) + + /* [mapping:log] */ + *(.literal.esp_log_write .text.esp_log_write) + *(.literal.esp_log_timestamp .text.esp_log_timestamp) + *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *(.literal.esp_log_impl_lock .text.esp_log_impl_lock) + *(.literal.esp_log_impl_lock_timeout .text.esp_log_impl_lock_timeout) + *(.literal.esp_log_impl_unlock .text.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ + *libzephyr.a:spi_flash_chip_boya.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_gd.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_generic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_issi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_th.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_winbond.*(.literal .literal.* .text .text.*) + *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hpm_enable.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_oct_flash_init*(.literal .literal.* .text .text.*) + + /* [mapping:esp_system] */ + *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*) + *(.literal.esp_system_abort .text.esp_system_abort) + + /* [mapping:esp_hw_support] */ + *(.literal.esp_cpu_stall .text.esp_cpu_stall) + *(.literal.esp_cpu_unstall .text.esp_cpu_unstall) + *(.literal.esp_cpu_reset .text.esp_cpu_reset) + *(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr) + *(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set) + *(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins) + *(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved) + *(.literal.rtc_vddsdio_get_config .text.rtc_vddsdio_get_config) + *(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) + *libzephyr.a:systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:mspi_timing_config.*(.literal .literal.* .text .text.*) + *libzephyr.a:mspi_timing_tuning.*(.literal .literal.* .text .text.*) + *(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable) + + /* [mapping:soc_pm] */ + *(.literal.GPIO_HOLD_MASK .text.GPIO_HOLD_MASK) + + /* [mapping:esp_rom] */ + *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_wdt.*(.literal .literal.* .text .text.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*) + *libzephyr.a:cache_utils.*(.literal .text .literal.* .text.*) + +#if defined(CONFIG_ESP32_WIFI_IRAM_OPT) + *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) + *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) + *libcoexist.a:(.wifi_slp_iram .wifi_slp_iram.*) + + /* [mapping:esp_wifi] */ + *(.literal.wifi_clock_enable_wrapper .text.wifi_clock_enable_wrapper) + *(.literal.wifi_clock_disable_wrapper .text.wifi_clock_disable_wrapper) + + /* [mapping:esp_phy] */ + *(.literal.esp_phy_enable .text.esp_phy_enable) + *(.literal.esp_phy_disable .text.esp_phy_disable) + *(.literal.esp_wifi_bt_power_domain_off .text.esp_wifi_bt_power_domain_off) +#endif /* CONFIG_ESP32_WIFI_IRAM_OPT */ + +#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) + *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) + *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) +#endif /* CONFIG_ESP32_WIFI_RX_IRAM_OPT */ + + . = ALIGN(4) + 16; + + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + +#ifdef CONFIG_ESP_SIMPLE_BOOT + .loader.text : + { + . = ALIGN(4); + _loader_text_start = ABSOLUTE(.); + *libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_esp32c3.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_clock_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_wdt.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_flash_config_esp32c3.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_mem.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) + *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) + *libzephyr.a:bootloader_efuse.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*) + + *libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_ops.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_ops_esp32c3.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_common.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_flash_api.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_flash_spi_init.*(.literal .text .literal.* .text.*) + + *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) + + *libzephyr.a:cpu_region_protect.*(.literal .text .literal.* .text.*) + + /* ??? */ + *libzephyr.a:esp_gpio_reserve.*(.literal .text .literal.* .text.*) + + . = ALIGN(0x10) + 0x10; + _loader_text_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) +#endif /* CONFIG_ESP_SIMPLE_BOOT */ + + .iram0.text_end (NOLOAD) : + { + /* C3 memprot requires 512 B alignment for split lines */ + . = ALIGN (16); + _iram_text_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) + + .iram0.data : + { + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) + + /* --- END OF IRAM --- */ + + /* --- START OF DRAM --- */ + + .dram0.dummy (NOLOAD): + { + /* Spacer section is required to skip .iram0.text area because + * iram0_0_seg and dram0_0_seg reflect the same address space on different buses. + */ + . = ORIGIN(dram0_0_seg) + MAX(_iram_end, user_iram_seg_org) - user_iram_seg_org; + . = ALIGN(16) + 16; + } GROUP_LINK_IN(RAMABLE_REGION) + + .dram0.data : + { + . = ALIGN(4); + _data_start = ABSOLUTE(.); + __data_start = ABSOLUTE(.); + + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + +#ifdef CONFIG_RISCV_GP + . = ALIGN(8); + __global_pointer$ = . + 0x800; +#endif /* CONFIG_RISCV_GP */ + + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + + /* All dependent functions should be placed in DRAM to avoid issue + * when flash cache is disabled */ + *libkernel.a:fatal.*(.rodata .rodata.* .srodata .srodata.*) + *libkernel.a:init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:cbprintf_complete*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:log_core.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:log_backend_uart.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:log_output.*(.rodata .rodata.* .srodata .srodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.* .srodata .srodata.*) + *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:periph_ctrl.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:loader.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:cache_utils.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:hal] */ + *libzephyr.a:mmu_hal.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:cache_hal.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:systimer_hal.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:log] */ + *(.rodata.esp_log_write) + *(.rodata.esp_log_timestamp) + *(.rodata.esp_log_early_timestamp) + *(.rodata.esp_log_impl_lock) + *(.rodata.esp_log_impl_lock_timeout) + *(.rodata.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ + *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:memspi_host_driver.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hpm_enable.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_oct_flash_init.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:esp_hw_support] */ + *(.rodata.esp_cpu_stall) + *(.rodata.esp_cpu_unstall) + *(.rodata.esp_cpu_reset) + *(.rodata.esp_cpu_wait_for_intr) + *(.rodata.esp_cpu_compare_and_set) + *(.rodata.esp_gpio_reserve_pins) + *(.rodata.esp_gpio_is_pin_reserved) + *(.rodata.rtc_vddsdio_get_config) + *(.rodata.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:rtc_clk_init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:systimer.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:mspi_timing_config.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:mspi_timing_tuning.*(.rodata .rodata.* .srodata .srodata.*) + *(.rodata.sar_periph_ctrl_power_enable) + + /* [mapping:esp_system] */ + *libzephyr.a:esp_err.*(.rodata .rodata.*) + *(.rodata.esp_system_abort) + + . = ALIGN(4); + #include + . = ALIGN(4); + + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + +#ifdef CONFIG_ESP_SIMPLE_BOOT + /* Secondary loader sections */ + .loader.data : + { + . = ALIGN(4); + _loader_data_start = ABSOLUTE(.); + *libzephyr.a:bootloader_soc.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_esp32c3.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_clock_init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_wdt.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_flash.*(.srodata .srodata.* .rodata .rodata.*) + *libzephyr.a:bootloader_flash_config_esp32c3.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_clock_loader.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_common_loader.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_panic.*(.rodata .rodata.* .srodata .srodata.*) + + *libzephyr.a:cpu_region_protect.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:clk.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:esp_clk.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:flash_mmap.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:flash_ops.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:flash_ops_esp32c3.*(.rodata .rodata.* .srodata .srodata.*) + + *libzephyr.a:esp_gpio_reserve.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_common.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:esp_flash_api.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:esp_flash_spi_init.*(.rodata .rodata.* .srodata .srodata.*) + + . = ALIGN(16); + _loader_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) +#endif /* CONFIG_ESP_SIMPLE_BOOT */ + + #include + #include + #include + #include + + /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ + #pragma push_macro("GROUP_ROM_LINK_IN") + #undef GROUP_ROM_LINK_IN + #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN + #include + #pragma pop_macro("GROUP_ROM_LINK_IN") + + .dram0.end : + { + . = ALIGN(4); + _data_end = ABSOLUTE(.); + __data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + .dram0.noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + *(.noinit.*) + . = ALIGN(4); + } GROUP_LINK_IN(RAMABLE_REGION) + + /* Shared RAM */ + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + __bss_start = ABSOLUTE(.); + _bss_start = ABSOLUTE(.); + + /* bluetooth library requires this symbol to be defined */ + _btdm_bss_start = ABSOLUTE(.); + *libbtdm_app.a:(.bss .bss.* COMMON) + . = ALIGN (4); + _btdm_bss_end = ABSOLUTE(.); + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (16); + __bss_end = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) + + /* Provide total SRAM usage, including IRAM and DRAM */ + _image_ram_start = _iram_start - IRAM_DRAM_OFFSET; + #include + + ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") + + /* --- END OF DRAM --- */ + + /* --- START OF .rodata --- */ + + /* Align next section to 64k to allow mapping */ + .flash.rodata_dummy (NOLOAD) : + { + . = ALIGN(CACHE_ALIGN); + } GROUP_LINK_IN(ROMABLE_REGION) + + /* Symbols used during the application memory mapping */ + _image_drom_start = LOADADDR(.flash.rodata); + _image_drom_size = LOADADDR(.flash.rodata_end) + SIZEOF(.flash.rodata_end) - _image_drom_start; + _image_drom_vaddr = ADDR(.flash.rodata); + + .flash.rodata : ALIGN(0x10) { _rodata_reserved_start = ABSOLUTE(.); _rodata_start = ABSOLUTE(.); @@ -141,10 +663,6 @@ SECTIONS . = ALIGN(4); #include - . = ALIGN(4); - *(EXCLUDE_FILE (*libarch__riscv__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata) - *(EXCLUDE_FILE (*libarch__riscv__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata.*) - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ *(.gnu.linkonce.r.*) *(.rodata1) @@ -184,6 +702,7 @@ SECTIONS . = ALIGN(4); } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + #include #include #include #include @@ -196,236 +715,54 @@ SECTIONS /* Create an explicit section at the end of all the data that shall be mapped into drom. * This is used to calculate the size of the _image_drom_size variable */ - SECTION_PROLOGUE(_RODATA_SECTION_END,,) + .flash.rodata_end : ALIGN(0x10) { - _rodata_reserved_end = ABSOLUTE(.); . = ALIGN(4); + _rodata_reserved_end = ABSOLUTE(.); _image_rodata_end = ABSOLUTE(.); } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - .iram0.text : ALIGN(4) - { - /* Vectors go to IRAM */ - _iram_start = ABSOLUTE(.); - _init_start = ABSOLUTE(.); + /* --- END OF .rodata --- */ - KEEP(*(.exception_vectors.text)); - . = ALIGN(256); - - _invalid_pc_placeholder = ABSOLUTE(.); - - _iram_text_start = ABSOLUTE(.); - - KEEP(*(.exception.entry*)); /* contains _isr_wrapper */ - *(.exception.other*) - . = ALIGN(4); - - *(.entry.text) - *(.init.literal) - *(.init) - . = ALIGN(4); - *(.iram1 .iram1.*) - *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - *libesp32.a:panic.*(.literal .text .literal.* .text.*) - *librtc.a:(.literal .text .literal.* .text.*) - *libarch__riscv__core.a:(.literal .text .literal.* .text.*) - *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*) - *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*) - *libsubsys__net__ip.a:(.literal .text .literal.* .text.*) - *libsubsys__net.a:(.literal .text .literal.* .text.*) - *libkernel.a:(.literal .text .literal.* .text.*) - *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) - *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) - *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) - *libdrivers__timer.a:esp32_sys_timer.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) - *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) - *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) - *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) - *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) - *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) - *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) - *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) - *libzephyr.a:loader.*(.literal .text .literal.* .text.*) - *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) - *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) - *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) - *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) - *libc.a:*(.literal .text .literal.* .text.*) - *libphy.a:( .phyiram .phyiram.*) - *libgcov.a:(.literal .text .literal.* .text.*) - -#if defined(CONFIG_ESP32_WIFI_IRAM_OPT) - *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) - *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) -#endif - -#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) - *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) - *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) -#endif - . = ALIGN(4); - _init_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - .dram0.dummy (NOLOAD): - { - /** - * This section is required to skip .iram0.text area because iram0_0_seg and - * dram0_0_seg reflect the same address space on different buses. - */ - . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; - } GROUP_LINK_IN(RAMABLE_REGION) - - /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) - { - . = ALIGN (8); - __bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - __bss_end = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) - - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) - { - . = ALIGN(4); - *(.noinit) - *(.noinit.*) - . = ALIGN(4); - } GROUP_LINK_IN(RAMABLE_REGION) - - .dram0.data : - { - . = ALIGN(4); - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) -#ifdef CONFIG_RISCV_GP - __global_pointer$ = . + 0x800; -#endif /* CONFIG_RISCV_GP */ - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - - /* All dependent functions should be placed in DRAM to avoid issue - * when flash cache is disabled */ - *libkernel.a:fatal.*(.rodata .rodata.*) - *libkernel.a:init.*(.rodata .rodata.*) - *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) - *libzephyr.a:log_core.*(.rodata .rodata.*) - *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) - *libzephyr.a:log_output.*(.rodata .rodata.*) - *libzephyr.a:cache_hal.*(.rodata .rodata.*) - *libzephyr.a:mmu_hal.*(.rodata .rodata.*) - *libzephyr.a:loader.*(.rodata .rodata.*) - *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) - *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) - *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) - - - KEEP(*(.jcr)) - *(.dram1 .dram1.*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - #include - #include - #include - #include - #include - #include - - /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ - #pragma push_macro("GROUP_ROM_LINK_IN") - #undef GROUP_ROM_LINK_IN - #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN - #include - #pragma pop_macro("GROUP_ROM_LINK_IN") - - .dummy.dram.data : - { - . = ALIGN(4); - #include - _end = ABSOLUTE(.); - _data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - .iram0.text_end (NOLOAD) : - { - /* C3 memprot requires 512 B alignment for split lines */ - . = ALIGN (16); - } GROUP_LINK_IN(IRAM_REGION) - - .iram0.data : - { - . = ALIGN(16); - *(.iram.data) - *(.iram.data*) - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - .iram0.bss (NOLOAD) : - { - . = ALIGN(16); - *(.iram.bss) - *(.iram.bss*) - - . = ALIGN(16); - _iram_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_REGION) + /* --- START OF .flash.text --- */ + /* Symbols used during the application memory mapping */ _image_irom_start = LOADADDR(.flash.text); _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; _image_irom_vaddr = ADDR(.flash.text); - .flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN) + .flash.text_dummy (NOLOAD): { - . = SIZEOF(_RODATA_SECTION_NAME); - . = ALIGN(0x10000) + 0x20; - } GROUP_LINK_IN(FLASH_CODE_REGION) + /* Spacer in the IROM address to avoid interfering with the DROM address + * because DROM and IROM regions share the same address space */ + . += _image_rodata_end - _rodata_start; + . = ALIGN(CACHE_ALIGN); + } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) - .flash.text : ALIGN(IROM_SEG_ALIGN) + .flash.text : ALIGN(CACHE_ALIGN) { _stext = .; _instruction_reserved_start = ABSOLUTE(.); _text_start = ABSOLUTE(.); + _instruction_reserved_start = ABSOLUTE(.); #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) -#endif +#endif /* CONFIG_ESP32_WIFI_IRAM_OPT */ #if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) -#endif +#endif /* CONFIG_ESP32_WIFI_RX_IRAM_OPT */ *(.literal .text .literal.* .text.*) *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) *(.fini) + *(.gnu.version) /** CPU will try to prefetch up to 16 bytes of @@ -435,6 +772,7 @@ SECTIONS */ . += 16; + _instruction_reserved_end = ABSOLUTE(.); _text_end = ABSOLUTE(.); _instruction_reserved_end = ABSOLUTE(.); _etext = .; @@ -444,63 +782,16 @@ SECTIONS * resolved by addr2line in preference to the first symbol in * the flash.text segment. */ - _flash_cache_start = ABSOLUTE(0); + //_flash_cache_start = ABSOLUTE(0); } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) - .rtc.text : - { - . = ALIGN(4); - *(.rtc.literal .rtc.text) - *rtc_wake_stub*.o(.literal .text .literal.* .text.*) - } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) - - /* This section is required to skip rtc.text area because the text and - * data segments reflect the same address space on different buses. - */ - .rtc.dummy (NOLOAD): - { - . = SIZEOF(.rtc.text); - } GROUP_LINK_IN(rtc_iram_seg) - - .rtc.data : - { - _rtc_data_start = ABSOLUTE(.); - *(.rtc.data) - *(.rtc.rodata) - *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) - _rtc_data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) - - .rtc.bss (NOLOAD) : - { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.o(.bss .bss.*) - *rtc_wake_stub*.o(COMMON) - _rtc_bss_end = ABSOLUTE(.); - } GROUP_LINK_IN(rtc_iram_seg) - - /** - * This section located in RTC SLOW Memory area. - * It holds data marked with RTC_SLOW_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_slow : - { - . = ALIGN(4); - _rtc_force_slow_start = ABSOLUTE(.); - *(.rtc.force_slow .rtc.force_slow.*) - . = ALIGN(4) ; - _rtc_force_slow_end = ABSOLUTE(.); - } > rtc_slow_seg - - /* Get size of rtc slow data */ - _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); + /* --- END OF .flash.text --- */ #ifdef CONFIG_GEN_ISR_TABLES -#include + #include #endif -#include + #include /DISCARD/ : { *(.note.GNU-stack) } SECTION_PROLOGUE(.riscv.attributes, 0,) diff --git a/soc/espressif/esp32c3/mcuboot.ld b/soc/espressif/esp32c3/mcuboot.ld index 958018168e1..8f402f566be 100644 --- a/soc/espressif/esp32c3/mcuboot.ld +++ b/soc/espressif/esp32c3/mcuboot.ld @@ -1,20 +1,15 @@ /* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. * SPDX-License-Identifier: Apache-2.0 */ -/** - * @file - * @brief Linker command/script file - * - * Linker script for the esp32c3 platform. - */ - #include #include #include #include +#include "memory.h" + #ifdef CONFIG_XIP #error "ESP32C3 bootloader cannot use XIP" #endif /* CONFIG_XIP */ @@ -24,20 +19,18 @@ #define GROUP_DATA_LINK_IN(vregion, lregion) > vregion #define RAMABLE_REGION dram_seg -#define RODATA_REGION dram_seg - -#define IRAM_REGION iram_seg -#define IRAM_LOADER_REGION iram_loader_seg - +#define RODATA_REGION dram_seg #define ROMABLE_REGION dram_seg -#define IROM_SEG_ALIGN 0x4 /* Global symbols required for espressif hal build */ MEMORY { - iram_seg (RX) : org = 0x403CA000, len = 0x9000 - iram_loader_seg (RX) : org = 0x403D3000, len = 0x4000 - dram_seg (RW) : org = 0x3FCD8000, len = 0x9000 + iram_seg (RX) : org = BOOTLOADER_IRAM_SEG_START, + len = BOOTLOADER_IRAM_SEG_LEN + iram_loader_seg (RX) : org = BOOTLOADER_IRAM_LOADER_SEG_START, + len = BOOTLOADER_IRAM_LOADER_SEG_LEN + dram_seg (RW) : org = BOOTLOADER_DRAM_SEG_START, + len = BOOTLOADER_DRAM_SEG_LEN #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 @@ -49,15 +42,135 @@ ENTRY(CONFIG_KERNEL_ENTRY) SECTIONS { - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) + .iram0.loader_text : { - _rodata_start = ABSOLUTE(.); + . = ALIGN (16); + _loader_text_start = ABSOLUTE(.); + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + + /* TODO: cross-segments calls in the libzephyr.a:device.* */ + + *libapp.a:flash_map_extended.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_nano.*(.literal .text .literal.* .text.*) + *libzephyr.a:cpu.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_map.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*) + + *libzephyr.a:heap.*(.literal .text .literal.* .text.*) + + *libkernel.a:kheap.*(.literal .text .literal.* .text.*) + *libkernel.a:mempool.*(.literal .text .literal.* .text.*) + + *(.literal.bootloader_mmap .text.bootloader_mmap) + *(.literal.bootloader_munmap .text.bootloader_munmap) + + *libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + + *(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*) + *(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler) + *(.literal.esp_log_timestamp .text.esp_log_timestamp) + *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *(.literal.esp_system_abort .text.esp_system_abort) + + *(.fini.literal) + *(.fini) + *(.gnu.version) + _loader_text_end = ABSOLUTE(.); + _iram_end = ABSOLUTE(.); + } > iram_loader_seg + + .iram0.text : + { + /* Vectors go to IRAM */ + _iram_start = ABSOLUTE(.); + _init_start = ABSOLUTE(.); + + KEEP(*(.exception_vectors.text)); + . = ALIGN(256); + + _invalid_pc_placeholder = ABSOLUTE(.); + + _iram_text_start = ABSOLUTE(.); + + KEEP(*(.exception.entry*)); /* contains _isr_wrapper */ + *(.exception.other*) + . = ALIGN(4); + + *(.entry.text) + *(.init.literal) + *(.init) + . = ALIGN(4); + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + + /* C3 memprot requires 512 B alignment for split lines */ + . = ALIGN (16); + _init_end = ABSOLUTE(.); + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + + *(.literal .text .literal.* .text.*) + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + + /* CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + + _text_end = ABSOLUTE(.); + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } > iram_seg + + .dram0.data : + { + . = ALIGN(4); + __data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) +#ifdef CONFIG_RISCV_GP + __global_pointer$ = . + 0x800; +#endif /* CONFIG_RISCV_GP */ + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + . = ALIGN(4); + + #include + . = ALIGN(4); *(.rodata_desc .rodata_desc.*) *(.rodata_custom_desc .rodata_custom_desc.*) - __rodata_region_start = .; - . = ALIGN(4); #include . = ALIGN(4); @@ -108,39 +221,14 @@ SECTIONS _thread_local_end = ABSOLUTE(.); /* _rodata_reserved_end = ABSOLUTE(.); */ . = ALIGN(4); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + } > dram_seg #include #include #include #include - #include - .dram0.data : - { - . = ALIGN(4); - __data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) -#ifdef CONFIG_RISCV_GP - __global_pointer$ = . + 0x800; -#endif /* CONFIG_RISCV_GP */ - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - *libzephyr.a:mmu_hal.*(.rodata .rodata.*) - *libzephyr.a:rtc_clk.*(.rodata .rodata.*) - KEEP(*(.jcr)) - *(.dram1 .dram1.*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - #include #include #include @@ -150,17 +238,16 @@ SECTIONS #include - .dram0.end : + .noinit (NOLOAD): { . = ALIGN(4); - #include + *(.noinit) + *(.noinit.*) . = ALIGN(4); - _end = ABSOLUTE(.); - __data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + } > dram_seg /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + .bss (NOLOAD): { . = ALIGN (8); _bss_start = ABSOLUTE(.); @@ -182,155 +269,13 @@ SECTIONS . = ALIGN (8); __bss_end = ABSOLUTE(.); _bss_end = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) - - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) - { - . = ALIGN(4); - *(.noinit) - *(.noinit.*) - . = ALIGN(4); - } GROUP_LINK_IN(RAMABLE_REGION) - - .iram_loader.text : - { - . = ALIGN (16); - _loader_text_start = ABSOLUTE(.); - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ - *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_flash_config_esp32c3.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_init_common.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) - *libzephyr.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) - *libzephyr.a:bootloader_efuse_esp32c3.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_console.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*) - *libzephyr.a:bootloader_soc.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) - *libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) - *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) - *libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*) - *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*) - *esp_mcuboot.*(.literal .text .literal.* .text.*) - *esp_loader.*(.literal .text .literal.* .text.*) - *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) - *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) - *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) - *(.fini.literal) - *(.fini) - *(.gnu.version) - _loader_text_end = ABSOLUTE(.); - } > iram_loader_seg - - /* .iram0.text : ALIGN(4) */ - SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4)) - { - /* Vectors go to IRAM */ - _iram_start = ABSOLUTE(.); - _init_start = ABSOLUTE(.); - - KEEP(*(.exception_vectors.text)); - . = ALIGN(256); - - _invalid_pc_placeholder = ABSOLUTE(.); - - _iram_text_start = ABSOLUTE(.); - - KEEP(*(.exception.entry*)); /* contains _isr_wrapper */ - *(.exception.other*) - . = ALIGN(4); - - *(.entry.text) - *(.init.literal) - *(.init) - . = ALIGN(4); - *(.iram1 .iram1.*) - *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - - . = ALIGN(4); - _init_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(IRAM_LOADER_REGION, ROMABLE_REGION) - - .iram0.text_end (NOLOAD) : - { - /* C3 memprot requires 512 B alignment for split lines */ - . = ALIGN (16); - } GROUP_LINK_IN(IRAM_LOADER_REGION) - - .iram0.data : - { - . = ALIGN(16); - *(.iram.data) - *(.iram.data*) - } GROUP_DATA_LINK_IN(IRAM_LOADER_REGION, ROMABLE_REGION) - - .iram0.bss (NOLOAD) : - { - . = ALIGN(16); - *(.iram.bss) - *(.iram.bss*) - - . = ALIGN(16); - _iram_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_LOADER_REGION) - - .flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN) - { - . = SIZEOF(_RODATA_SECTION_NAME); - . = ALIGN(4) + 0x20; - _rodata_reserved_start = .; - } GROUP_LINK_IN(IRAM_REGION) - - .flash.text : ALIGN(IROM_SEG_ALIGN) - { - _stext = .; - _text_start = ABSOLUTE(.); - - *(.literal .text .literal.* .text.*) - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - - /* CPU will try to prefetch up to 16 bytes of - * of instructions. This means that any configuration (e.g. MMU, PMS) must allow - * safe access to up to 16 bytes after the last real instruction, add - * dummy bytes to ensure this - */ - . += 16; - - _text_end = ABSOLUTE(.); - _etext = .; - - /* Similar to _iram_start, this symbol goes here so it is - * resolved by addr2line in preference to the first symbol in - * the flash.text segment. - */ - _flash_cache_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + } > dram_seg /* linker rel sections*/ #include #ifdef CONFIG_GEN_ISR_TABLES -#include + #include #endif #include diff --git a/soc/espressif/esp32c3/memory.h b/soc/espressif/esp32c3/memory.h new file mode 100644 index 00000000000..f249f8b9643 --- /dev/null +++ b/soc/espressif/esp32c3/memory.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +/* SRAM0 (16kB) memory */ +#define SRAM0_IRAM_START 0x4037c000 +#define SRAM0_SIZE 0x4000 +/* SRAM1 (384kB) memory */ +#define SRAM1_DRAM_START 0x3fc80000 +#define SRAM1_IRAM_START 0x40380000 +/* ICache size is fixed to 16KB on ESP32-C3 */ +#define ICACHE_SIZE SRAM0_SIZE + +/** Simplified memory map for the bootloader. + * Make sure the bootloader can load into main memory without overwriting itself. + * + * ESP32-C3 ROM static data usage is as follows: + * - 0x3fccae00 - 0x3fcdc710: Shared buffers, used in UART/USB/SPI download mode only + * - 0x3fcdc710 - 0x3fcde710: PRO CPU stack, can be reclaimed as heap after RTOS startup + * - 0x3fcde710 - 0x3fce0000: ROM .bss and .data (not easily reclaimable) + * + * The 2nd stage bootloader can take space up to the end of ROM shared + * buffers area (0x3fcdc710). + */ + +/* The offset between Dbus and Ibus. + * Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. + */ +#define IRAM_DRAM_OFFSET 0x700000 +#define DRAM_BUFFERS_START 0x3fccae00 +#define DRAM_STACK_START 0x3fcdc710 +#define DRAM_ROM_BSS_DATA_START 0x3fcde710 + +/* Base address used for calculating memory layout + * counted from Dbus backwards and back to the Ibus + */ +#define BOOTLOADER_USABLE_DRAM_END DRAM_BUFFERS_START + +/* For safety margin between bootloader data section and startup stacks */ +#define BOOTLOADER_STACK_OVERHEAD 0x0 +/* These lengths can be adjusted, if necessary: */ +#define BOOTLOADER_DRAM_SEG_LEN 0x9000 +#define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x3000 +#define BOOTLOADER_IRAM_SEG_LEN 0x8000 + +/* Start of the lower region is determined by region size and the end of the higher region */ +#define BOOTLOADER_DRAM_SEG_END (BOOTLOADER_USABLE_DRAM_END + BOOTLOADER_STACK_OVERHEAD) +#define BOOTLOADER_DRAM_SEG_START (BOOTLOADER_DRAM_SEG_END - BOOTLOADER_DRAM_SEG_LEN) +#define BOOTLOADER_IRAM_LOADER_SEG_START (BOOTLOADER_DRAM_SEG_START - \ + BOOTLOADER_IRAM_LOADER_SEG_LEN + IRAM_DRAM_OFFSET) +#define BOOTLOADER_IRAM_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN) + +/* Flash */ +#ifdef CONFIG_FLASH_SIZE +#define FLASH_SIZE CONFIG_FLASH_SIZE +#else +#define FLASH_SIZE 0x400000 +#endif + +/* Cached memory */ +#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE +#define IROM_SEG_ORG 0x42000000 +#define IROM_SEG_LEN FLASH_SIZE +#define DROM_SEG_ORG 0x3c000000 +#define DROM_SEG_LEN FLASH_SIZE diff --git a/soc/espressif/esp32c3/soc.c b/soc/espressif/esp32c3/soc.c index c25f188da89..cb13c6205af 100644 --- a/soc/espressif/esp32c3/soc.c +++ b/soc/espressif/esp32c3/soc.c @@ -43,17 +43,6 @@ extern void esp_reset_reason_init(void); */ void __attribute__((section(".iram1"))) __esp_platform_start(void) { -#ifdef CONFIG_RISCV_GP - /* Configure the global pointer register - * (This should be the first thing startup does, as any other piece of code could be - * relaxed by the linker to access something relative to __global_pointer$) - */ - __asm__ __volatile__(".option push\n" - ".option norelax\n" - "la gp, __global_pointer$\n" - ".option pop"); -#endif /* CONFIG_RISCV_GP */ - __asm__ __volatile__("la t0, _esp32c3_vector_table\n" "csrw mtvec, t0\n"); @@ -64,12 +53,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) esp_reset_reason_init(); -#ifdef CONFIG_MCUBOOT - /* MCUboot early initialisation. - */ - bootloader_init(); - -#else +#ifndef CONFIG_MCUBOOT /* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence * related issues in application. Hence disable that as we are about to start * Zephyr environment. @@ -103,13 +87,13 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) #ifdef CONFIG_SOC_FLASH_ESP32 esp_mspi_pin_init(); - /** - * This function initialise the Flash chip to the user-defined settings. - * - * In bootloader, we only init Flash (and MSPI) to a preliminary state, for being flexible to - * different chips. - * In this stage, we re-configure the Flash (and MSPI) to required configuration - */ + /** + * This function initialise the Flash chip to the user-defined settings. + * + * In bootloader, we only init Flash (and MSPI) to a preliminary + * state, for being flexible to different chips. + * In this stage, we re-configure the Flash (and MSPI) to required configuration + */ spi_flash_init_chip_state(); esp_mmu_map_init(); @@ -127,7 +111,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) spi_flash_guard_set(&g_flash_guard_default_ops); #endif -#endif /* CONFIG_MCUBOOT */ +#endif /* !CONFIG_MCUBOOT */ /*Initialize the esp32c3 interrupt controller */ esp_intr_initialize();