pcie: add initial controller support
This adds : - Generic PCIe Controller layer implementing the current PCIe API - Generic PCIe Controller in ECAM mode driver The Generic PCIe Controller layer provides: - Configuration space read/write - single bus endpoint enumerations - Endpoint I/O, MEM & MEM64 BARs allocation - Endpoint I/O, MEM & MEM64 BARs get & translation for drivers The Generic PCIe Controller in ECAM mode driver provides: - Raw DT RANGES properties into usable PCIe regions - Configuration space read/write into ECAM config space - PCIe regions allocation & translation The limitations are: - No support for PCIe prefetchable regions - No support for PCIe bus configuration (only bus0 is supported) - No support for multiple controllers (no domain-id in BDF) Support has been designed to initially support Root Complexes with Root Complex Integrated Endpoint, which was designed for Embedded Systems with internal-only PCIe Endpoints on bus 0. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong
Carles Cufí
parent
c714368691
commit
f8f2936dba
6 changed files with 580 additions and 4 deletions
293
drivers/pcie/host/pcie_ecam.c
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293
drivers/pcie/host/pcie_ecam.c
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@ -0,0 +1,293 @@
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/*
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* Copyright (c) 2021 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pcie_ecam, LOG_LEVEL_ERR);
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#include <kernel.h>
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#include <device.h>
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#include <drivers/pcie/pcie.h>
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#include <drivers/pcie/controller.h>
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#define DT_DRV_COMPAT pci_host_ecam_generic
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/*
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* PCIe Controllers Regions
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*
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* TOFIX:
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* - handle prefetchable regions
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*/
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enum pcie_region_type {
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PCIE_REGION_IO = 0,
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PCIE_REGION_MEM,
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PCIE_REGION_MEM64,
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PCIE_REGION_MAX,
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};
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struct pcie_ecam_data {
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uintptr_t cfg_phys_addr;
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mm_reg_t cfg_addr;
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size_t cfg_size;
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struct {
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uintptr_t phys_start;
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uintptr_t bus_start;
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size_t size;
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size_t allocation_offset;
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} regions[PCIE_REGION_MAX];
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};
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static int pcie_ecam_init(const struct device *dev)
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{
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const struct pcie_ctrl_config *cfg = (const struct pcie_ctrl_config *)dev->config;
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struct pcie_ecam_data *data = (struct pcie_ecam_data *)dev->data;
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int i;
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/*
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* Flags defined in the PCI Bus Binding to IEEE Std 1275-1994 :
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* Bit# 33222222 22221111 11111100 00000000
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* 10987654 32109876 54321098 76543210
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*
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* phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
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* phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
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* phys.lo cell: llllllll llllllll llllllll llllllll
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*
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* where:
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*
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* n is 0 if the address is relocatable, 1 otherwise
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* p is 1 if the addressable region is "prefetchable", 0 otherwise
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* t is 1 if the address is aliased (for non-relocatable I/O), below 1 MB (for Memory),
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* or below 64 KB (for relocatable I/O).
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* ss is the space code, denoting the address space
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* 00 denotes Configuration Space
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* 01 denotes I/O Space
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* 10 denotes 32-bit-address Memory Space
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* 11 denotes 64-bit-address Memory Space
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* bbbbbbbb is the 8-bit Bus Number
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* ddddd is the 5-bit Device Number
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* fff is the 3-bit Function Number
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* rrrrrrrr is the 8-bit Register Number
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* hh...hh is a 32-bit unsigned number
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* ll...ll is a 32-bit unsigned number
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* for I/O Space is the 32-bit offset from the start of the region
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* for 32-bit-address Memory Space is the 32-bit offset from the start of the region
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* for 64-bit-address Memory Space is the 64-bit offset from the start of the region
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*
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* Here we only handle the p, ss, hh and ll fields.
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*
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* TOFIX:
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* - handle prefetchable bit
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*/
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for (i = 0 ; i < cfg->ranges_count ; ++i) {
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switch ((cfg->ranges[i].flags >> 24) & 0x03) {
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case 0x01:
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data->regions[PCIE_REGION_IO].bus_start = cfg->ranges[i].pcie_bus_addr;
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data->regions[PCIE_REGION_IO].phys_start = cfg->ranges[i].host_map_addr;
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data->regions[PCIE_REGION_IO].size = cfg->ranges[i].map_length;
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/* Linux & U-Boot avoids allocating PCI resources from address 0 */
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if (data->regions[PCIE_REGION_IO].bus_start < 0x1000)
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data->regions[PCIE_REGION_IO].allocation_offset = 0x1000;
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break;
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case 0x02:
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data->regions[PCIE_REGION_MEM].bus_start = cfg->ranges[i].pcie_bus_addr;
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data->regions[PCIE_REGION_MEM].phys_start = cfg->ranges[i].host_map_addr;
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data->regions[PCIE_REGION_MEM].size = cfg->ranges[i].map_length;
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/* Linux & U-Boot avoids allocating PCI resources from address 0 */
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if (data->regions[PCIE_REGION_MEM].bus_start < 0x1000)
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data->regions[PCIE_REGION_MEM].allocation_offset = 0x1000;
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break;
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case 0x03:
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data->regions[PCIE_REGION_MEM64].bus_start = cfg->ranges[i].pcie_bus_addr;
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data->regions[PCIE_REGION_MEM64].phys_start = cfg->ranges[i].host_map_addr;
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data->regions[PCIE_REGION_MEM64].size = cfg->ranges[i].map_length;
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/* Linux & U-Boot avoids allocating PCI resources from address 0 */
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if (data->regions[PCIE_REGION_MEM64].bus_start < 0x1000)
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data->regions[PCIE_REGION_MEM64].allocation_offset = 0x1000;
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break;
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}
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}
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if (!data->regions[PCIE_REGION_IO].size &&
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!data->regions[PCIE_REGION_MEM].size &&
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!data->regions[PCIE_REGION_MEM64].size) {
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LOG_ERR("No regions defined");
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return -EINVAL;
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}
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/* Get Config address space physical address & size */
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data->cfg_phys_addr = cfg->cfg_addr;
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data->cfg_size = cfg->cfg_size;
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if (data->regions[PCIE_REGION_IO].size) {
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LOG_DBG("IO bus [0x%lx - 0x%lx, size 0x%lx]",
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data->regions[PCIE_REGION_IO].bus_start,
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(data->regions[PCIE_REGION_IO].bus_start +
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data->regions[PCIE_REGION_IO].size - 1),
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data->regions[PCIE_REGION_IO].size);
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LOG_DBG("IO space [0x%lx - 0x%lx, size 0x%lx]",
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data->regions[PCIE_REGION_IO].phys_start,
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(data->regions[PCIE_REGION_IO].phys_start +
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data->regions[PCIE_REGION_IO].size - 1),
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data->regions[PCIE_REGION_IO].size);
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}
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if (data->regions[PCIE_REGION_MEM].size) {
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LOG_DBG("MEM bus [0x%lx - 0x%lx, size 0x%lx]",
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data->regions[PCIE_REGION_MEM].bus_start,
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(data->regions[PCIE_REGION_MEM].bus_start +
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data->regions[PCIE_REGION_MEM].size - 1),
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data->regions[PCIE_REGION_MEM].size);
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LOG_DBG("MEM space [0x%lx - 0x%lx, size 0x%lx]",
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data->regions[PCIE_REGION_MEM].phys_start,
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(data->regions[PCIE_REGION_MEM].phys_start +
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data->regions[PCIE_REGION_MEM].size - 1),
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data->regions[PCIE_REGION_MEM].size);
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}
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if (data->regions[PCIE_REGION_MEM64].size) {
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LOG_DBG("MEM64 bus [0x%lx - 0x%lx, size 0x%lx]",
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data->regions[PCIE_REGION_MEM64].bus_start,
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(data->regions[PCIE_REGION_MEM64].bus_start +
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data->regions[PCIE_REGION_MEM64].size - 1),
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data->regions[PCIE_REGION_MEM64].size);
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LOG_DBG("MEM64 space [0x%lx - 0x%lx, size 0x%lx]",
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data->regions[PCIE_REGION_MEM64].phys_start,
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(data->regions[PCIE_REGION_MEM64].phys_start +
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data->regions[PCIE_REGION_MEM64].size - 1),
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data->regions[PCIE_REGION_MEM64].size);
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}
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/* Map config space to be used by the generic_pcie_ctrl_conf_read/write callbacks */
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device_map(&data->cfg_addr, data->cfg_phys_addr, data->cfg_size, K_MEM_CACHE_NONE);
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LOG_DBG("Config space [0x%lx - 0x%lx, size 0x%lx]",
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data->cfg_phys_addr, (data->cfg_phys_addr + data->cfg_size - 1), data->cfg_size);
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LOG_DBG("Config mapped [0x%lx - 0x%lx, size 0x%lx]",
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data->cfg_addr, (data->cfg_addr + data->cfg_size - 1), data->cfg_size);
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generic_pcie_ctrl_enumerate(dev, PCIE_BDF(0, 0, 0));
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return 0;
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}
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static uint32_t pcie_ecam_ctrl_conf_read(const struct device *dev, pcie_bdf_t bdf, unsigned int reg)
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{
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struct pcie_ecam_data *data = (struct pcie_ecam_data *)dev->data;
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return generic_pcie_ctrl_conf_read(data->cfg_addr, bdf, reg);
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}
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static void pcie_ecam_ctrl_conf_write(const struct device *dev, pcie_bdf_t bdf, unsigned int reg,
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uint32_t reg_data)
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{
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struct pcie_ecam_data *data = (struct pcie_ecam_data *)dev->data;
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generic_pcie_ctrl_conf_write(data->cfg_addr, bdf, reg, reg_data);
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}
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static bool pcie_ecam_region_allocate_type(struct pcie_ecam_data *data, pcie_bdf_t bdf,
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size_t bar_size, uintptr_t *bar_bus_addr,
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enum pcie_region_type type)
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{
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uintptr_t addr;
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addr = (((data->regions[type].bus_start + data->regions[type].allocation_offset) - 1) |
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((bar_size) - 1)) + 1;
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if (addr - data->regions[type].bus_start + bar_size > data->regions[type].size)
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return false;
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*bar_bus_addr = addr;
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data->regions[type].allocation_offset = addr - data->regions[type].bus_start + bar_size;
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return true;
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}
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static bool pcie_ecam_region_allocate(const struct device *dev, pcie_bdf_t bdf,
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bool mem, bool mem64, size_t bar_size,
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uintptr_t *bar_bus_addr)
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{
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struct pcie_ecam_data *data = (struct pcie_ecam_data *)dev->data;
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enum pcie_region_type type;
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if (mem && !data->regions[PCIE_REGION_MEM64].size &&
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!data->regions[PCIE_REGION_MEM].size) {
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LOG_DBG("bdf %x no mem region defined for allocation", bdf);
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return false;
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}
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if (!mem && !data->regions[PCIE_REGION_IO].size) {
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LOG_DBG("bdf %x no io region defined for allocation", bdf);
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return false;
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}
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/*
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* Allocate into mem64 region if available or is the only available
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*
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* TOFIX:
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* - handle allocation from/to mem/mem64 when a region is full
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*/
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if (mem && ((mem64 && data->regions[PCIE_REGION_MEM64].size) ||
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(data->regions[PCIE_REGION_MEM64].size &&
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!data->regions[PCIE_REGION_MEM].size))) {
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type = PCIE_REGION_MEM64;
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} else if (mem) {
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type = PCIE_REGION_MEM;
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} else {
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type = PCIE_REGION_IO;
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}
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return pcie_ecam_region_allocate_type(data, bdf, bar_size, bar_bus_addr, type);
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}
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static bool pcie_ecam_region_xlate(const struct device *dev, pcie_bdf_t bdf,
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bool mem, bool mem64, uintptr_t bar_bus_addr,
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uintptr_t *bar_addr)
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{
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struct pcie_ecam_data *data = (struct pcie_ecam_data *)dev->data;
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enum pcie_region_type type;
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/* Means it hasn't been allocated */
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if (!bar_bus_addr)
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return false;
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if (mem && ((mem64 && data->regions[PCIE_REGION_MEM64].size) ||
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(data->regions[PCIE_REGION_MEM64].size &&
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!data->regions[PCIE_REGION_MEM].size))) {
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type = PCIE_REGION_MEM64;
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} else if (mem) {
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type = PCIE_REGION_MEM;
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} else {
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type = PCIE_REGION_IO;
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}
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*bar_addr = data->regions[type].phys_start + (bar_bus_addr - data->regions[type].bus_start);
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return true;
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}
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static const struct pcie_ctrl_driver_api pcie_ecam_api = {
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.conf_read = pcie_ecam_ctrl_conf_read,
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.conf_write = pcie_ecam_ctrl_conf_write,
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.region_allocate = pcie_ecam_region_allocate,
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.region_xlate = pcie_ecam_region_xlate,
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};
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#define PCIE_ECAM_INIT(n) \
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static struct pcie_ecam_data pcie_ecam_data##n; \
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static const struct pcie_ctrl_config pcie_ecam_config##n = { \
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.cfg_addr = DT_INST_REG_ADDR(n), \
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.cfg_size = DT_INST_REG_SIZE(n), \
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.ranges_count = DT_NUM_RANGES(DT_DRV_INST(n)), \
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.ranges = { \
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DT_FOREACH_RANGE(DT_DRV_INST(n), PCIE_RANGE_FORMAT) \
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}, \
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}; \
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DEVICE_DT_INST_DEFINE(n, &pcie_ecam_init, NULL, \
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&pcie_ecam_data##n, \
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&pcie_ecam_config##n, \
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PRE_KERNEL_1, \
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
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&pcie_ecam_api);
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DT_INST_FOREACH_STATUS_OKAY(PCIE_ECAM_INIT)
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