michaelh/zephyr
1
0
Fork 0
Code Releases Activity

xtensa: add support for thread local storage

Browse source 
Adds the necessary bits to initialize TLS in the stack
area and sets up CPU registers during context switch.

Note that this does not enable TLS for all Xtensa SoC.
This is because Xtensa SoCs are highly configurable
so that each SoC can be considered a whole architecture.
So TLS needs to be enabled on the SoC level, instead of
at the arch level.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2020-10-02 14:55:34 -07:00 • committed by Andrew Boie
commit f8a909dad1
8 changed files with 88 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

4
arch/xtensa/include/xtensa-asm2-s.h
View file

@ -114,6 +114,10 @@
rsr.SCOMPARE1 a0
s32i a0, a1, BSA_SCOMPARE1_OFF
#endif
#if XCHAL_HAVE_THREADPTR && defined(CONFIG_THREAD_LOCAL_STORAGE)
rur.THREADPTR a0
s32i a0, a1, BSA_THREADPTR_OFF
#endif
.endm
/*