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espi: updated MEC172x espi module for pinctrl

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Changes to espi module to support pinctrl

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
This commit is contained in:
Jay Vasanth 2022-01-21 12:15:27 -05:00 • committed by Carles Cufí
commit f8130d5ce3
3 changed files with 24 additions and 3 deletions
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14
drivers/espi/espi_mchp_xec_v2.c
View file

@ -1207,13 +1207,17 @@ static const struct espi_xec_irq_info espi_xec_irq_info_0[] = {
DT_FOREACH_PROP_ELEM(DT_NODELABEL(espi0), girqs, XEC_IRQ_INFO) DT_FOREACH_PROP_ELEM(DT_NODELABEL(espi0), girqs, XEC_IRQ_INFO)
}; };
/* pin control structure(s) */
PINCTRL_DT_INST_DEFINE(0);
static const struct espi_xec_config espi_xec_config = { static const struct espi_xec_config espi_xec_config = {
.base_addr = DT_INST_REG_ADDR(0), .base_addr = DT_INST_REG_ADDR(0),
.vw_base_addr = DT_INST_REG_ADDR_BY_NAME(0, vw), .vw_base_addr = DT_INST_REG_ADDR_BY_NAME(0, vw),
.pcr_idx = DT_INST_PROP_BY_IDX(0, pcrs, 0), .pcr_idx = DT_INST_PROP_BY_IDX(0, pcrs, 0),
.pcr_bitpos = DT_INST_PROP_BY_IDX(0, pcrs, 1), .pcr_bitpos = DT_INST_PROP_BY_IDX(0, pcrs, 1),
.irq_info_list = espi_xec_irq_info_0,
.irq_info_size = ARRAY_SIZE(espi_xec_irq_info_0), .irq_info_size = ARRAY_SIZE(espi_xec_irq_info_0),
.irq_info_list = espi_xec_irq_info_0,
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
}; };
DEVICE_DT_INST_DEFINE(0, &espi_xec_init, NULL, DEVICE_DT_INST_DEFINE(0, &espi_xec_init, NULL,
@ -1288,6 +1292,8 @@ static void espi_xec_connect_irqs(const struct device *dev)
* contains the state of 4 virtual wires. * contains the state of 4 virtual wires.
* The total supported virtual wires is 64 * 4 = 256. * The total supported virtual wires is 64 * 4 = 256.
* MEC172x supports 11 MSVW groups and 11 SMVW groups. * MEC172x supports 11 MSVW groups and 11 SMVW groups.
* NOTE: While ESPI_nRESET is active most of the eSPI hardware is held
* in reset state.
*/ */
static int espi_xec_init(const struct device *dev) static int espi_xec_init(const struct device *dev)
{ {
@ -1297,6 +1303,12 @@ static int espi_xec_init(const struct device *dev)
struct pcr_regs *pcr = XEC_PCR_REG_BASE; struct pcr_regs *pcr = XEC_PCR_REG_BASE;
int ret; int ret;
ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
LOG_ERR("XEC eSPI V2 pinctrl setup failed (%d)", ret);
return ret;
}
data->plt_rst_asserted = 0; data->plt_rst_asserted = 0;
#ifdef ESPI_XEC_V2_DEBUG #ifdef ESPI_XEC_V2_DEBUG
data->espi_rst_count = 0; data->espi_rst_count = 0;

5
drivers/espi/espi_mchp_xec_v2.h
View file

@ -10,6 +10,7 @@
#include <stdint.h> #include <stdint.h>
#include <device.h> #include <device.h>
#include <drivers/espi.h> #include <drivers/espi.h>
#include <drivers/pinctrl.h>
#define ESPI_XEC_V2_DEBUG 1 #define ESPI_XEC_V2_DEBUG 1
@ -38,8 +39,10 @@ struct espi_xec_config {
uint32_t vw_base_addr; uint32_t vw_base_addr;
uint8_t pcr_idx; uint8_t pcr_idx;
uint8_t pcr_bitpos; uint8_t pcr_bitpos;
const struct espi_xec_irq_info *irq_info_list;
uint8_t irq_info_size; uint8_t irq_info_size;
uint8_t rsvd[1];
const struct espi_xec_irq_info *irq_info_list;
const struct pinctrl_dev_config *pcfg;
}; };
#define ESPI_XEC_CONFIG(dev) \ #define ESPI_XEC_CONFIG(dev) \

8
dts/bindings/espi/microchip,xec-espi-v2.yaml
View file

@ -6,7 +6,7 @@ description: Microchip ESPI V2 controller
compatible: "microchip,xec-espi-v2" compatible: "microchip,xec-espi-v2"
include: espi-controller.yaml include: [espi-controller.yaml, pinctrl-device.yaml]
properties: properties:
reg: reg:
@ -28,6 +28,12 @@ properties:
required: true required: true
description: eSPI PCR register index and bit position description: eSPI PCR register index and bit position
pinctrl-0:
required: true
pinctrl-names:
required: true
"#girq-cells": "#girq-cells":
type: int type: int
const: 1 const: 1