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soc: arm: stm32g0: Add PM support

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Low power modes for the STM32G0 series.

Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This commit is contained in:
Yong Cong Sin 2021-06-21 18:36:57 +08:00 • committed by Anas Nashif
commit f7ba9ce226
3 changed files with 113 additions and 0 deletions
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5
soc/arm/st_stm32/stm32g0/CMakeLists.txt
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@ -1,6 +1,11 @@
# Copyright (c) 2021 G-Technologies Sdn. Bhd.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(${ZEPHYR_BASE}/drivers) zephyr_include_directories(${ZEPHYR_BASE}/drivers)
zephyr_sources( zephyr_sources(
soc.c soc.c
) )
zephyr_sources_ifdef(CONFIG_PM
power.c
)

9
soc/arm/st_stm32/stm32g0/Kconfig.defconfig.series
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@ -2,6 +2,7 @@
# Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com> # Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
# Copyright (c) 2019 STMicroelectronics # Copyright (c) 2019 STMicroelectronics
# Copyright (c) 2021 G-Technologies Sdn. Bhd.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_STM32G0X if SOC_SERIES_STM32G0X
@ -11,4 +12,12 @@ source "soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0*"
config SOC_SERIES config SOC_SERIES
default "stm32g0" default "stm32g0"
if PM
config PM_DEVICE
default y
config STM32_LPTIM_TIMER
default y
endif # PM
endif # SOC_SERIES_STM32G0X endif # SOC_SERIES_STM32G0X

99
soc/arm/st_stm32/stm32g0/power.c Normal file
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@ -0,0 +1,99 @@
/*
* Copyright (c) 2021 STMicroelectronics.
* Copyright (c) 2021 G-Technologies Sdn. Bhd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr.h>
#include <pm/pm.h>
#include <soc.h>
#include <init.h>
#include <stm32g0xx_ll_utils.h>
#include <stm32g0xx_ll_bus.h>
#include <stm32g0xx_ll_cortex.h>
#include <stm32g0xx_ll_pwr.h>
#include <stm32g0xx_ll_system.h>
#include <clock_control/clock_stm32_ll_common.h>
#include <logging/log.h>
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
/* Invoke Low Power/System Off specific Tasks */
void pm_power_state_set(struct pm_state_info info)
{
if (info.state != PM_STATE_SUSPEND_TO_IDLE) {
LOG_DBG("Unsupported power state %u", info.state);
return;
}
switch (info.substate_id) {
case 1: /* this corresponds to the STOP0 mode: */
/* enter STOP0 mode */
LL_PWR_SetPowerMode(LL_PWR_MODE_STOP0);
LL_LPM_EnableDeepSleep();
/* enter SLEEP mode : WFE or WFI */
k_cpu_idle();
break;
case 2: /* this corresponds to the STOP1 mode: */
/* enter STOP1 mode */
LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1);
LL_LPM_EnableDeepSleep();
/* enter SLEEP mode : WFE or WFI */
k_cpu_idle();
break;
default:
LOG_DBG("Unsupported power state substate-id %u",
info.substate_id);
break;
}
}
/* Handle SOC specific activity after Low Power Mode Exit */
void pm_power_state_exit_post_ops(struct pm_state_info info)
{
if (info.state != PM_STATE_SUSPEND_TO_IDLE) {
LOG_DBG("Unsupported power substate %u", info.state);
} else {
switch (info.substate_id) {
case 1: /* STOP0 */
__fallthrough;
case 2: /* STOP1 */
LL_LPM_DisableSleepOnExit();
/* Clear SLEEPDEEP bit */
LL_LPM_EnableSleep();
break;
default:
LOG_DBG("Unsupported power substate-id %u",
info.substate_id);
break;
}
/* need to restore the clock */
stm32_clock_control_init(NULL);
}
/*
* System is now in active mode.
* Reenable interrupts which were disabled
* when OS started idling code.
*/
irq_unlock(0);
}
/* Initialize STM32 Power */
static int stm32_power_init(const struct device *dev)
{
ARG_UNUSED(dev);
/* enable Power clock */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
#ifdef CONFIG_DEBUG
/* Enable the Debug Module during all and any Low power mode */
LL_DBGMCU_EnableDBGStopMode();
#endif /* CONFIG_DEBUG */
return 0;
}
SYS_INIT(stm32_power_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);