diff --git a/soc/arm/st_stm32/stm32g0/CMakeLists.txt b/soc/arm/st_stm32/stm32g0/CMakeLists.txt
index ac3ba70ace6..aff2873dc18 100644
--- a/soc/arm/st_stm32/stm32g0/CMakeLists.txt
+++ b/soc/arm/st_stm32/stm32g0/CMakeLists.txt
@@ -1,6 +1,11 @@
+# Copyright (c) 2021 G-Technologies Sdn. Bhd.
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(${ZEPHYR_BASE}/drivers)
 zephyr_sources(
   soc.c
   )
+
+zephyr_sources_ifdef(CONFIG_PM
+  power.c
+  )
diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.series
index 039b6900cc6..8501075bbe7 100644
--- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.series
+++ b/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.series
@@ -2,6 +2,7 @@
 
 # Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
 # Copyright (c) 2019 STMicroelectronics
+# Copyright (c) 2021 G-Technologies Sdn. Bhd.
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_STM32G0X
@@ -11,4 +12,12 @@ source "soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0*"
 config SOC_SERIES
 	default "stm32g0"
 
+if PM
+config PM_DEVICE
+	default y
+
+config STM32_LPTIM_TIMER
+	default y
+endif # PM
+
 endif # SOC_SERIES_STM32G0X
diff --git a/soc/arm/st_stm32/stm32g0/power.c b/soc/arm/st_stm32/stm32g0/power.c
new file mode 100644
index 00000000000..3039bf663f8
--- /dev/null
+++ b/soc/arm/st_stm32/stm32g0/power.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2021 G-Technologies Sdn. Bhd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr.h>
+#include <pm/pm.h>
+#include <soc.h>
+#include <init.h>
+
+#include <stm32g0xx_ll_utils.h>
+#include <stm32g0xx_ll_bus.h>
+#include <stm32g0xx_ll_cortex.h>
+#include <stm32g0xx_ll_pwr.h>
+#include <stm32g0xx_ll_system.h>
+#include <clock_control/clock_stm32_ll_common.h>
+
+#include <logging/log.h>
+LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
+
+/* Invoke Low Power/System Off specific Tasks */
+void pm_power_state_set(struct pm_state_info info)
+{
+	if (info.state != PM_STATE_SUSPEND_TO_IDLE) {
+		LOG_DBG("Unsupported power state %u", info.state);
+		return;
+	}
+
+	switch (info.substate_id) {
+	case 1: /* this corresponds to the STOP0 mode: */
+		/* enter STOP0 mode */
+		LL_PWR_SetPowerMode(LL_PWR_MODE_STOP0);
+		LL_LPM_EnableDeepSleep();
+		/* enter SLEEP mode : WFE or WFI */
+		k_cpu_idle();
+		break;
+	case 2: /* this corresponds to the STOP1 mode: */
+		/* enter STOP1 mode */
+		LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1);
+		LL_LPM_EnableDeepSleep();
+		/* enter SLEEP mode : WFE or WFI */
+		k_cpu_idle();
+		break;
+	default:
+		LOG_DBG("Unsupported power state substate-id %u",
+			info.substate_id);
+		break;
+	}
+}
+
+/* Handle SOC specific activity after Low Power Mode Exit */
+void pm_power_state_exit_post_ops(struct pm_state_info info)
+{
+	if (info.state != PM_STATE_SUSPEND_TO_IDLE) {
+		LOG_DBG("Unsupported power substate %u", info.state);
+	} else {
+		switch (info.substate_id) {
+		case 1:	/* STOP0 */
+			__fallthrough;
+		case 2:	/* STOP1 */
+			LL_LPM_DisableSleepOnExit();
+			/* Clear SLEEPDEEP bit */
+			LL_LPM_EnableSleep();
+			break;
+		default:
+			LOG_DBG("Unsupported power substate-id %u",
+				info.substate_id);
+			break;
+		}
+		/* need to restore the clock */
+		stm32_clock_control_init(NULL);
+	}
+
+	/*
+	 * System is now in active mode.
+	 * Reenable interrupts which were disabled
+	 * when OS started idling code.
+	 */
+	irq_unlock(0);
+}
+
+/* Initialize STM32 Power */
+static int stm32_power_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* enable Power clock */
+	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
+
+#ifdef CONFIG_DEBUG
+	/* Enable the Debug Module during all and any Low power mode */
+	LL_DBGMCU_EnableDBGStopMode();
+#endif /* CONFIG_DEBUG */
+
+	return 0;
+}
+
+SYS_INIT(stm32_power_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);