From f6f2e57ab96fc880a4592fc63a93db4b9767202c Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Wed, 5 Feb 2025 18:03:21 +0100 Subject: [PATCH] soc: renesas: ra: ra6m5: clear NVIC->ITNS at startup for non TZ Otherwise, interrupts will trigger a very funny fault See https://github.com/arduino/ArduinoCore-renesas/blob/main/cores/arduino/main.cpp#L49-L57 Signed-off-by: Martino Facchin --- soc/renesas/ra/ra6m5/soc.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/soc/renesas/ra/ra6m5/soc.c b/soc/renesas/ra/ra6m5/soc.c index 872b89421d3..87d4b090b5c 100644 --- a/soc/renesas/ra/ra6m5/soc.c +++ b/soc/renesas/ra/ra6m5/soc.c @@ -57,9 +57,16 @@ void soc_early_init_hook(void) R_PSCU->PSARD = 0; R_PSCU->PSARE = 0; - R_CPSCU->ICUSARG = 0; - R_CPSCU->ICUSARH = 0; - R_CPSCU->ICUSARI = 0; + /* The secure Attribute managed within the ARM CPU NVIC must match the + * security attribution of IELSEn registers (Reference section 13.2.9 + * in the RA6M4 manual R01UH0890EJ0050). + */ + uint32_t volatile *p_icusarg = &R_CPSCU->ICUSARG; + + for (int i = 0; i < BSP_ICU_VECTOR_MAX_ENTRIES / NUM_BITS(uint32_t); i++) { + p_icusarg[i] = 0; + NVIC->ITNS[i] = 0; + } /* Enable protection using PRCR register. */ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);