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soc: nxp: k6x: move clk divider options to device tree

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Use kinetis SIM clock divider options set in device tree
instead of kconfig

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
This commit is contained in:
Mikkel Jakobsen 2021-03-02 17:57:04 +01:00 • committed by Maureen Helm
commit f674e82ac4
3 changed files with 38 additions and 33 deletions
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29
dts/arm/nxp/nxp_k6x.dtsi
View file

@ -107,8 +107,35 @@
compatible = "nxp,kinetis-sim";
reg = <0x40047000 0x1060>;
label = "SIM";
#clock-cells = <3>;
core_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <1>;
#clock-cells = <0>;
};
bus_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <2>;
#clock-cells = <0>;
};
flexbus_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <3>;
#clock-cells = <0>;
};
flash_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <5>;
#clock-cells = <0>;
};
};
ftfe: flash-controller@40020000 {

28
soc/arm/nxp_kinetis/k6x/Kconfig.soc
View file

@ -91,34 +91,6 @@ config SOC_PART_NUMBER_KINETIS_K6X
that you should not set directly. The part number selection choice defines
the default value for this string.
config K6X_CORE_CLOCK_DIVIDER
int "Freescale K6X core clock divider"
default 1
help
This option specifies the divide value for the K6X processor core clock
from the system clock.
config K6X_BUS_CLOCK_DIVIDER
int "Freescale K6X bus clock divider"
default 2
help
This option specifies the divide value for the K6X bus clock from the
system clock.
config K6X_FLEXBUS_CLOCK_DIVIDER
int "Freescale K6X FlexBus clock divider"
default 3
help
This option specifies the divide value for the K6X FlexBus clock from the
system clock.
config K6X_FLASH_CLOCK_DIVIDER
int "Freescale K6X flash clock divider"
default 5
help
This option specifies the divide value for the K6X flash clock from the
system clock.
config K6X_HSRUN
bool "High Speed RUN mode"
depends on SOC_MK66F18

14
soc/arm/nxp_kinetis/k6x/soc.c
View file

@ -27,6 +27,12 @@
#define RUNM_HSRUN (3)
#define CLOCK_NODEID(clk) \
DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
#define CLOCK_DIVIDER(clk) \
DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
static const osc_config_t oscConfig = {
.freq = CONFIG_OSC_XTAL0_FREQ,
.capLoad = 0,
@ -59,10 +65,10 @@ static const mcg_pll_config_t pll0Config = {
static const sim_clock_config_t simConfig = {
.pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_K6X_CORE_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV2(CONFIG_K6X_BUS_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV3(CONFIG_K6X_FLEXBUS_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV4(CONFIG_K6X_FLASH_CLOCK_DIVIDER - 1),
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |
SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
};
/**