From f674e82ac486b8d4b3e0d4558eda019fc350dab7 Mon Sep 17 00:00:00 2001 From: Mikkel Jakobsen Date: Tue, 2 Mar 2021 17:57:04 +0100 Subject: [PATCH] soc: nxp: k6x: move clk divider options to device tree Use kinetis SIM clock divider options set in device tree instead of kconfig Signed-off-by: Mikkel Jakobsen --- dts/arm/nxp/nxp_k6x.dtsi | 29 ++++++++++++++++++++++++++++- soc/arm/nxp_kinetis/k6x/Kconfig.soc | 28 ---------------------------- soc/arm/nxp_kinetis/k6x/soc.c | 14 ++++++++++---- 3 files changed, 38 insertions(+), 33 deletions(-) diff --git a/dts/arm/nxp/nxp_k6x.dtsi b/dts/arm/nxp/nxp_k6x.dtsi index 1b70aebc93e..a09c3ea68ba 100644 --- a/dts/arm/nxp/nxp_k6x.dtsi +++ b/dts/arm/nxp/nxp_k6x.dtsi @@ -107,8 +107,35 @@ compatible = "nxp,kinetis-sim"; reg = <0x40047000 0x1060>; label = "SIM"; - #clock-cells = <3>; + + core_clk { + compatible = "fixed-factor-clock"; + clocks = <&mcg KINETIS_MCG_OUT_CLK>; + clock-div = <1>; + #clock-cells = <0>; + }; + + bus_clk { + compatible = "fixed-factor-clock"; + clocks = <&mcg KINETIS_MCG_OUT_CLK>; + clock-div = <2>; + #clock-cells = <0>; + }; + + flexbus_clk { + compatible = "fixed-factor-clock"; + clocks = <&mcg KINETIS_MCG_OUT_CLK>; + clock-div = <3>; + #clock-cells = <0>; + }; + + flash_clk { + compatible = "fixed-factor-clock"; + clocks = <&mcg KINETIS_MCG_OUT_CLK>; + clock-div = <5>; + #clock-cells = <0>; + }; }; ftfe: flash-controller@40020000 { diff --git a/soc/arm/nxp_kinetis/k6x/Kconfig.soc b/soc/arm/nxp_kinetis/k6x/Kconfig.soc index c05fb5a3eff..37884105a0d 100644 --- a/soc/arm/nxp_kinetis/k6x/Kconfig.soc +++ b/soc/arm/nxp_kinetis/k6x/Kconfig.soc @@ -91,34 +91,6 @@ config SOC_PART_NUMBER_KINETIS_K6X that you should not set directly. The part number selection choice defines the default value for this string. -config K6X_CORE_CLOCK_DIVIDER - int "Freescale K6X core clock divider" - default 1 - help - This option specifies the divide value for the K6X processor core clock - from the system clock. - -config K6X_BUS_CLOCK_DIVIDER - int "Freescale K6X bus clock divider" - default 2 - help - This option specifies the divide value for the K6X bus clock from the - system clock. - -config K6X_FLEXBUS_CLOCK_DIVIDER - int "Freescale K6X FlexBus clock divider" - default 3 - help - This option specifies the divide value for the K6X FlexBus clock from the - system clock. - -config K6X_FLASH_CLOCK_DIVIDER - int "Freescale K6X flash clock divider" - default 5 - help - This option specifies the divide value for the K6X flash clock from the - system clock. - config K6X_HSRUN bool "High Speed RUN mode" depends on SOC_MK66F18 diff --git a/soc/arm/nxp_kinetis/k6x/soc.c b/soc/arm/nxp_kinetis/k6x/soc.c index 65f4f96a586..f4ea9452725 100644 --- a/soc/arm/nxp_kinetis/k6x/soc.c +++ b/soc/arm/nxp_kinetis/k6x/soc.c @@ -27,6 +27,12 @@ #define RUNM_HSRUN (3) +#define CLOCK_NODEID(clk) \ + DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk) + +#define CLOCK_DIVIDER(clk) \ + DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1 + static const osc_config_t oscConfig = { .freq = CONFIG_OSC_XTAL0_FREQ, .capLoad = 0, @@ -59,10 +65,10 @@ static const mcg_pll_config_t pll0Config = { static const sim_clock_config_t simConfig = { .pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select), .er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select), - .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_K6X_CORE_CLOCK_DIVIDER - 1) | - SIM_CLKDIV1_OUTDIV2(CONFIG_K6X_BUS_CLOCK_DIVIDER - 1) | - SIM_CLKDIV1_OUTDIV3(CONFIG_K6X_FLEXBUS_CLOCK_DIVIDER - 1) | - SIM_CLKDIV1_OUTDIV4(CONFIG_K6X_FLASH_CLOCK_DIVIDER - 1), + .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) | + SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) | + SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) | + SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)), }; /**