From f668474e4d5fa378612699a850dd351356e85d62 Mon Sep 17 00:00:00 2001 From: Immo Birnbaum Date: Thu, 15 Jul 2021 13:05:54 +0200 Subject: [PATCH] soc: arm: dts: arm: xilinx: Zynq-7000 SoC init code, device tree data Add SoC-specific code, the basic device tree and Kconfig data as well as the corresponding linker command file for the Xilinx Zynq-7000 family of SoCs. This SoC - either as a QEMU simulation or on actual hardware such as the Avnet/Digilent ZedBoard - is suitable as an ini- tial target for the ARMv7 Cortex-A support. Signed-off-by: Immo Birnbaum --- CODEOWNERS | 1 + dts/arm/armv7-a.dtsi | 16 +++ dts/arm/xilinx/zynq7000.dtsi | 139 ++++++++++++++++++++++ soc/arm/xilinx_zynq7000/CMakeLists.txt | 9 ++ soc/arm/xilinx_zynq7000/Kconfig.defconfig | 25 ++++ soc/arm/xilinx_zynq7000/Kconfig.soc | 25 ++++ soc/arm/xilinx_zynq7000/linker.ld | 7 ++ soc/arm/xilinx_zynq7000/soc.c | 85 +++++++++++++ soc/arm/xilinx_zynq7000/soc.h | 20 ++++ 9 files changed, 327 insertions(+) create mode 100644 dts/arm/armv7-a.dtsi create mode 100644 dts/arm/xilinx/zynq7000.dtsi create mode 100644 soc/arm/xilinx_zynq7000/CMakeLists.txt create mode 100644 soc/arm/xilinx_zynq7000/Kconfig.defconfig create mode 100644 soc/arm/xilinx_zynq7000/Kconfig.soc create mode 100644 soc/arm/xilinx_zynq7000/linker.ld create mode 100644 soc/arm/xilinx_zynq7000/soc.c create mode 100644 soc/arm/xilinx_zynq7000/soc.h diff --git a/CODEOWNERS b/CODEOWNERS index e154695da38..d8b28facda9 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -433,6 +433,7 @@ /dts/riscv/starfive/ @rajnesh-kanwal /dts/riscv/andes_v5* @cwshu @Teng-Shih-Wei /dts/arm/armv*m.dtsi @galak @ioannisg +/dts/arm/armv7-a.dtsi @ibirnbaum /dts/arm/armv7-r.dtsi @bbolen @stephanosio /dts/arm/xilinx/ @bbolen @stephanosio /dts/arm/renesas/ @julien-massot diff --git a/dts/arm/armv7-a.dtsi b/dts/arm/armv7-a.dtsi new file mode 100644 index 00000000000..814c85187db --- /dev/null +++ b/dts/arm/armv7-a.dtsi @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2018 Lexmark International, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "skeleton.dtsi" + +/ { + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + }; +}; diff --git a/dts/arm/xilinx/zynq7000.dtsi b/dts/arm/xilinx/zynq7000.dtsi new file mode 100644 index 00000000000..18cf4ec029d --- /dev/null +++ b/dts/arm/xilinx/zynq7000.dtsi @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + }; + + soc { + interrupt-parent = <&gic>; + + ocm_low: memory@1000 { + compatible = "xlnx,zynq-ocm"; + reg = <0x00001000 DT_SIZE_K(188)>; + }; + + ocm_high: memory@fffc0000 { + compatible = "xlnx,zynq-ocm"; + reg = <0xFFFC0000 DT_SIZE_K(256)>; + }; + + arch_timer: timer@f8f00200 { + compatible = "arm,armv8-timer"; + status = "okay"; + interrupt-names = "irq_0", "irq_1", "irq_2", "irq_3"; + interrupts = , + , + , + ; + reg = <0xf8f00200 0x1C>; + label = "arch_timer"; + }; + + gic: interrupt-controller@f8f01000 { + compatible = "arm,gic"; + status = "okay"; + reg = <0xf8f01000 0x1000>, + <0xf8f00100 0x100>; + interrupt-controller; + #interrupt-cells = <4>; + label = "gic"; + }; + + gem0: ethernet@e000b000 { + compatible = "xlnx,gem"; + status = "disabled"; + reg = <0xe000b000 0x1000>, + <0xf8000140 0x4>; + interrupts = , + ; + interrupt-names = "irq_0", "irq_1"; + label = "gem0"; + mdio-phy-address = ; + phy-poll-interval = <1000>; + link-speed = ; + amba-ahb-dbus-width = ; + amba-ahb-burst-length = ; + hw-rx-buffer-size = ; + hw-rx-buffer-offset = <0>; + hw-tx-buffer-size-full; + rx-buffer-descriptors = <32>; + tx-buffer-descriptors = <32>; + rx-buffer-size = <512>; + tx-buffer-size = <512>; + discard-rx-fcs; + unicast-hash; + full-duplex; + }; + + gem1: ethernet@e000c000 { + compatible = "xlnx,gem"; + status = "disabled"; + reg = <0xe000c000 0x1000>, + <0xf8000144 0x4>; + interrupts = , + ; + interrupt-names = "irq_0", "irq_1"; + label = "gem1"; + mdio-phy-address = ; + phy-poll-interval = <1000>; + link-speed = ; + amba-ahb-dbus-width = ; + amba-ahb-burst-length = ; + hw-rx-buffer-size = ; + hw-rx-buffer-offset = <0>; + hw-tx-buffer-size-full; + rx-buffer-descriptors = <32>; + tx-buffer-descriptors = <32>; + rx-buffer-size = <512>; + tx-buffer-size = <512>; + discard-rx-fcs; + unicast-hash; + full-duplex; + }; + + uart0: uart@e0000000 { + compatible = "xlnx,xuartps"; + status = "disabled"; + reg = <0xe0000000 0x4c>; + interrupts = ; + interrupt-names = "irq_0"; + label = "uart0"; + }; + + uart1: uart@e0001000 { + compatible = "xlnx,xuartps"; + status = "disabled"; + reg = <0xe0001000 0x4c>; + interrupts = ; + interrupt-names = "irq_0"; + label = "uart1"; + }; + + }; +}; diff --git a/soc/arm/xilinx_zynq7000/CMakeLists.txt b/soc/arm/xilinx_zynq7000/CMakeLists.txt new file mode 100644 index 00000000000..d2544510f42 --- /dev/null +++ b/soc/arm/xilinx_zynq7000/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources( + soc.c +) diff --git a/soc/arm/xilinx_zynq7000/Kconfig.defconfig b/soc/arm/xilinx_zynq7000/Kconfig.defconfig new file mode 100644 index 00000000000..5671ef2a289 --- /dev/null +++ b/soc/arm/xilinx_zynq7000/Kconfig.defconfig @@ -0,0 +1,25 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_XILINX_ZYNQ7000 || SOC_XILINX_ZYNQ7000S + +config SOC + default "xilinx_zynq7000" + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 96 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +endif diff --git a/soc/arm/xilinx_zynq7000/Kconfig.soc b/soc/arm/xilinx_zynq7000/Kconfig.soc new file mode 100644 index 00000000000..4b8ce5bc9a4 --- /dev/null +++ b/soc/arm/xilinx_zynq7000/Kconfig.soc @@ -0,0 +1,25 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_XILINX_ZYNQ7000 + bool "Xilinx Zynq-7000 Core Series" + select ARM + select CPU_CORTEX_A9 + select GIC_V1 + select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER + help + Enable support for the Xilinx Zynq-7000 SoC series. + +choice + prompt "Xilinx Zynq-7000 Selection" + depends on SOC_SERIES_XILINX_ZYNQ7000 + +config SOC_XILINX_ZYNQ7000 + bool "Xilinx Zynq-7000 dual-core (XC7Zxxx)" + +config SOC_XILINX_ZYNQ7000S + bool "Xilinx Zynq-7000 single-core (XC7ZxxxS)" + +endchoice diff --git a/soc/arm/xilinx_zynq7000/linker.ld b/soc/arm/xilinx_zynq7000/linker.ld new file mode 100644 index 00000000000..d0124975676 --- /dev/null +++ b/soc/arm/xilinx_zynq7000/linker.ld @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/xilinx_zynq7000/soc.c b/soc/arm/xilinx_zynq7000/soc.c new file mode 100644 index 00000000000..ecf8e34475d --- /dev/null +++ b/soc/arm/xilinx_zynq7000/soc.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include +#include "soc.h" + +static const struct arm_mmu_region mmu_regions[] = { + + MMU_REGION_FLAT_ENTRY("vectors", + 0x00000000, + 0x1000, + MT_STRONGLY_ORDERED | MPERM_R | MPERM_X), + MMU_REGION_FLAT_ENTRY("slcr", + 0xF8000000, + 0x1000, + MT_STRONGLY_ORDERED | MPERM_R | MPERM_W), + MMU_REGION_FLAT_ENTRY("mpcore", + 0xF8F00000, + 0x2000, + MT_STRONGLY_ORDERED | MPERM_R | MPERM_W), + MMU_REGION_FLAT_ENTRY("ocm", + DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)), + DT_REG_SIZE(DT_CHOSEN(zephyr_ocm)), + MT_STRONGLY_ORDERED | MPERM_R | MPERM_W), + /* ARM Arch timer, GIC are covered by the MPCore mapping */ +/* UARTs */ +#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart0), okay) + MMU_REGION_FLAT_ENTRY("uart0", + DT_REG_ADDR(DT_NODELABEL(uart0)), + DT_REG_SIZE(DT_NODELABEL(uart0)), + MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) + MMU_REGION_FLAT_ENTRY("uart1", + DT_REG_ADDR(DT_NODELABEL(uart1)), + DT_REG_SIZE(DT_NODELABEL(uart1)), + MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), +#endif + +/* GEMs */ +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gem0), okay) + MMU_REGION_FLAT_ENTRY("gem0", + DT_REG_ADDR(DT_NODELABEL(gem0)), + DT_REG_SIZE(DT_NODELABEL(gem0)), + MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gem1), okay) + MMU_REGION_FLAT_ENTRY("gem1", + DT_REG_ADDR(DT_NODELABEL(gem1)), + DT_REG_SIZE(DT_NODELABEL(gem1)), + MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), +#endif +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; + +/** + * @brief Basic hardware initialization of the Zynq-7000 SoC + * + * Performs the basic initialization of the Zynq-7000 SoC. + * + * @return 0 + */ +static int soc_xlnx_zynq7000_init(const struct device *arg) +{ + ARG_UNUSED(arg); + NMI_INIT(); + + return 0; +} + +SYS_INIT(soc_xlnx_zynq7000_init, PRE_KERNEL_1, + CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); + +/* EOF */ diff --git a/soc/arm/xilinx_zynq7000/soc.h b/soc/arm/xilinx_zynq7000/soc.h new file mode 100644 index 00000000000..5ce52301703 --- /dev/null +++ b/soc/arm/xilinx_zynq7000/soc.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#ifndef _ASMLANGUAGE + +/* + * The following definitions are required for the inclusion of the CMSIS + * Common Peripheral Access Layer for aarch32 Cortex-A CPUs: + */ + +#define __CORTEX_A 9U + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC__H_ */