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arm: dts: ti_lm3s6965: Add Device Tree Support

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Introduce a simple device tree for the TI lm3s6965 SoC and QEMU
Cortex-M3 board port.  We get flash and memory base addresses and sizes
from the device tree as well as the ARM NVIC number of priority bits.

Change-Id: I4452b5543de7be55518997e54837ccbfd4f121df
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-04-27 13:25:20 -05:00
commit f6284cfbec
6 changed files with 41 additions and 12 deletions
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10
arch/arm/soc/ti_lm3s6965/Kconfig.defconfig
View file

@ -11,16 +11,6 @@ if SOC_TI_LM3S6965
config SOC config SOC
default ti_lm3s6965 default ti_lm3s6965
config SRAM_BASE_ADDRESS
default 0x20000000
config FLASH_BASE_ADDRESS
default 0x00000000
config NUM_IRQ_PRIO_BITS
int
default 3
config NUM_IRQS config NUM_IRQS
int int
# must be >= the highest interrupt number used # must be >= the highest interrupt number used

3
boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig
View file

@ -6,6 +6,5 @@ CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_CORTEX_M_SYSTICK=y CONFIG_CORTEX_M_SYSTICK=y
CONFIG_FLASH_SIZE=256
CONFIG_SRAM_SIZE=64
CONFIG_UART_STELLARIS=y CONFIG_UART_STELLARIS=y
CONFIG_HAS_DTS=y

1
dts/arm/Makefile
View file

@ -28,6 +28,7 @@ dtb-$(CONFIG_BOARD_CURIE_BLE) = curie_ble.dts_compiled
dtb-$(CONFIG_BOARD_NRF51_BLENANO) = nrf51_blenano.dts_compiled dtb-$(CONFIG_BOARD_NRF51_BLENANO) = nrf51_blenano.dts_compiled
dtb-$(CONFIG_BOARD_NRF51_PCA10028) = nrf51_pca10028.dts_compiled dtb-$(CONFIG_BOARD_NRF51_PCA10028) = nrf51_pca10028.dts_compiled
dtb-$(CONFIG_BOARD_QUARK_SE_C1000_BLE) = quark_se_c1000_ble.dts_compiled dtb-$(CONFIG_BOARD_QUARK_SE_C1000_BLE) = quark_se_c1000_ble.dts_compiled
dtb-$(CONFIG_BOARD_QEMU_CORTEX_M3) = qemu_cortex_m3.dts_compiled
always := $(dtb-y) always := $(dtb-y)
endif endif

13
dts/arm/qemu_cortex_m3.dts Normal file
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@ -0,0 +1,13 @@
/dts-v1/;
#include <ti/lm3s6965.dtsi>
/ {
model = "QEMU Cortex-M3";
compatible = "ti,lm3s6965evb-qemu", "ti,lm3s6965";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
};

1
dts/arm/qemu_cortex_m3.fixup Normal file
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@ -0,0 +1 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS

25
dts/arm/ti/lm3s6965.dtsi Normal file
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@ -0,0 +1,25 @@
#include <arm/armv7-m.dtsi>
/ {
cpus {
cpu@0 {
compatible = "arm,cortex-m3";
};
};
sram0: memory {
compatible = "sram";
reg = <0x20000000 (64*1024)>;
};
flash0: flash {
reg = <0x00000000 (256*1024)>;
};
soc {
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};