f6284cfbec
Introduce a simple device tree for the TI lm3s6965 SoC and QEMU Cortex-M3 board port. We get flash and memory base addresses and sizes from the device tree as well as the ARM NVIC number of priority bits. Change-Id: I4452b5543de7be55518997e54837ccbfd4f121df Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
25 lines
286 B
Text
25 lines
286 B
Text
#include <arm/armv7-m.dtsi>
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/ {
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cpus {
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cpu@0 {
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compatible = "arm,cortex-m3";
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};
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};
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sram0: memory {
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compatible = "sram";
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reg = <0x20000000 (64*1024)>;
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};
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flash0: flash {
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reg = <0x00000000 (256*1024)>;
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};
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soc {
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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